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даташит 74VHC541-Q100 PDF ( Datasheet )

74VHC541-Q100 Datasheet Download - NXP

Номер произв 74VHC541-Q100
Описание Octal buffer/line driver
Производители NXP
логотип NXP логотип 

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74VHC541-Q100 Даташит, Описание, Даташиты
74VHC541-Q100;
74VHCT541-Q100
Octal buffer/line driver; 3-state
Rev. 1 — 4 June 2013
Product data sheet
1. General description
The 74VHC541-Q100; 74VHCT541-Q100 are high-speed Si-gate CMOS devices.
The 74VHC541-Q100; 74VHCT541-Q100 are octal non-inverting buffer/line drivers with
3-state bus compatible outputs.
The output enable inputs OE0 and OE1 control the 3-state outputs.
A HIGH on OEn causes the outputs to assume a high-impedance OFF-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than VCC
The 74VHC541-Q100 operates with CMOS input level
The 74VHCT541-Q100 operates with TTL input level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options







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74VHC541-Q100 Даташит, Описание, Даташиты
NXP Semiconductors
74VHC541-Q100; 74VHCT541-Q100
Octal buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74VHC541D-Q100 40 C to +125 C
74VHCT541D-Q100
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74VHC541PW-Q100 40 C to +125 C
74VHCT541PW-Q100
TSSOP20
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
74VHC541BQ-Q100 40 C to +125 C
74VHCT541BQ-Q100
DHVQFN20 plastic dual-in-line compatible thermal enhanced
very thin quad flat package; no leads; 20
terminals; body 2.5 4.5 0.85 mm
SOT764-1
4. Functional diagram
2 A0
3 A1
A2
4
A3
5
A4
6
A5
7
A6
8
9 A7
OE0
1
OE1
19
Fig 1. Logic symbol
Y0
18
Y1 17
Y2
16
Y3
15
Y4
14
Y5 13
Y6
12
Y7 11
mna179
1&
19 EN
2 18
3 17
4 16
5 15
6 14
7 13
8 12
9 11
mna180
Fig 2. IEC logic symbol
74VHC_VHCT541_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 June 2013
© NXP B.V. 2013. All rights reserved.
2 of 17







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74VHC541-Q100 Даташит, Описание, Даташиты
NXP Semiconductors
74VHC541-Q100; 74VHCT541-Q100
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
9+&4
9+&74
2( 
$ 
$ 
$ 
$ 
$ 
$ 
$ 
$ 
*1' 
 9&&
 2(
 <
 <
 <
 <
 <
 <
 <
 <
DDD
Fig 3. Pin configuration SO20, TSSOP20
9+&4
9+&74
WHUPLQDO
LQGH[DUHD
$ 
$ 
$ 
$ 
$ 
$ 
$ 
$ 
*1' 
 2(
 <
 <
 <
 <
 <
 <
 <
DDD
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE0
A[0:7]
GND
Y[0:7]
OE1
VCC
Pin description
Pin Description
1 output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8, 9
data input
10 ground (0 V)
18, 17, 16, 15, 14, 13, 12, 11 data output
19 output enable input (active LOW)
20 supply voltage
74VHC_VHCT541_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 4 June 2013
© NXP B.V. 2013. All rights reserved.
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