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PDF 74AC299 Data sheet ( Hoja de datos )
| Número de pieza | 74AC299 | |
| Descripción | 8 BIT PIPO SHIFT REGISTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74AC299
8 BIT PIPO SHIFT REGISTER
WITH ASYNCHRONOUS CLEAR
s HIGH SPEED:
s fMAX = 240MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
)VNIH = VNIL = 28 % VCC (MIN.)
t(ss 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
ucs SYMMETRICAL OUTPUT IMPEDANCE:
d|IOH| = IOL = 24mA (MIN)
ro )s BALANCED PROPAGATION DELAYS:
P t(stPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
lete ucVCC (OPR) = 2V to 6V
ds PIN AND FUNCTION COMPATIBLE WITH
so ro74 SERIES 299
b Ps IMPROVED LATCH-UP IMMUNITY
- O teDESCRIPTION
) leThe 74AC299 is an advanced high-speed CMOS
t(s o8-BIT PIPO SHIFT REGISTER (3-STATE)
sfabricated with sub-micron silicon gate and
c bdouble-layer metal wiring C2MOS technology.
du OThese devices have four modes (HOLD, SHIFT
ro -LEFT, SHIFT RIGHT and LOAD DATA). Each
P t(s)mode is chosen by two function select inputs (S0,
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC299B
74AC299M
T&R
74AC299MTR
74AC299TTR
S1) as shown in the Truth Table. When one or
both enable inputs, (G1, G2) are high, the eight
input/output terminals are in the high-impedance
state; however sequential operation or clearing of
the register is not affected. Clear function is
asynchronous to clock.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
OObbssoolleettee ProducPIN CONNECTION AND IEC LOGIC SYMBOLS
April 2001
1/13
1 page  
74AC299
DC SPECIFICATIONS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage
3.0
4.5
5.5
VO = 0.1 V or
VCC-0.1V
2.1 1.5
3.15 2.25
3.85 2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
VIL Low Level Input
Voltage
3.0
4.5
5.5
VO = 0.1 V or
VCC-0.1V
1.5 0.9 0.9 0.9
2.25 1.35
1.35
1.35 V
2.75 1.65
1.65
1.65
)VOH High Level Output 3.0
t(sVoltage
4.5
IO=-50 µA
IO=-50 µA
2.9 2.99
4.4 4.49
2.9
4.4
2.9
4.4
c5.5 IO=-50 µA 5.4 5.49
u3.0
IO=-12 mA
2.56
5.4
2.46
5.4
2.4
V
rod )4.5
IO=-24 mA
3.86
3.76
3.7
P t(s5.5
IO=-24 mA
4.86
4.76
4.7
te cVOL Low Level Output
le uVoltage
3.0
4.5
IO=50 µA
IO=50 µA
0.002 0.1 0.1 0.1
0.001 0.1 0.1 0.1
so rod5.5 IO=50 µA
3.0 IO=12 mA
0.001 0.1
0.36
0.1
0.44
0.1
V
0.5
b P4.5 IO=24 mA
0.36
0.44
0.5
- O te5.5 IO=24 mA
0.36
0.44
0.5
) leII Input Leakage
t(s oCurrent
5.5 VI = VCC or GND
± 0.1
±1
± 1 µA
sIoz High Impedance
c bOutput Leakage
u OCurrent
5.5
VI = VIH or VIL
VO = VCC or GND
± 0.5
±5
±10 µA
rod ) -ICC
Quiescent Supply
Current
5.5 VI = VCC or GND
8 80 160 µA
P t(sIOLD
te cIOHD
Dynamic Output
Current (note 1, 2)
5.5 VOLD = 1.65 V max
VOHD = 3.85 V min
le u1) Maximum test duration 2ms, one output loaded at time
OObbssoolete Prod2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
75
-75
50 mA
-50 mA
5/13
5 Page 
74AC299
SO-20 MECHANICAL DATA
DIM.
MIN.
mm
TYP.
MAX.
MIN.
inch
TYP.
MAX.
A 2.65 0.104
a1 0.10
0.20 0.004
0.007
a2 2.45 0.096
b 0.35
0.49 0.013
0.019
b1 0.23
0.32 0.009
0.012
t(s)C 0.50
0.020
cc1 45 (typ.)
uD 12.60
13.00
0.496
0.512
rod )E 10.00
10.65
0.393
0.419
P t(se 1.27
0.050
te ce3 11.43
0.450
le duF 7.40
7.60 0.291
0.299
so roL 0.50
1.27 0.19
0.050
b PM 0.75 0.029
OObbssoolleettee PPrroodduucctt((ss)) -- OObsoleteS 8(max.)
P013L
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74AC299.PDF ] | |
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