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PDF NTD4979N Data sheet ( Hoja de datos )
| Número de pieza | NTD4979N | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTD4979N
Power MOSFET
30 V, 41 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
TA = 100°C
VDSS
VGS
ID
30
±20
12.7
9.0
V
V
A
Power Dissipation
RqJA (Note 1)
Continuous Drain
Current RqJA
(Note 2)
Power Dissipation
RqJA (Note 2)
Continuous Drain
Current RqJC
(Note 1)
Steady
State
TA = 25°C
TA = 25°C
TA = 100°C
TA = 25°C
TC = 25°C
TC = 100°C
PD
ID
PD
ID
2.56 W
9.4 A
6.6
1.38 W
41 A
29
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
26.3 W
Pulsed Drain
Current
tp=10ms TA = 25°C
IDM
150 A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V,
IL = 19 Apk, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
IDmaxPkg
TJ,
TSTG
IS
dV/dt
EAS
40
−55 to
+175
24
6.0
18
A
°C
A
V/ns
mJ
TL 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
9.0 mW @ 10 V
19 mW @ 4.5 V
D
ID MAX
41 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
1 23
1
2
3
CASE 369AC CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
A = Assembly Location
Y = Year
WW = Work Week
4979N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 1
1
Publication Order Number:
NTD4979N/D
1 page  
NTD4979N
TYPICAL PERFORMANCE CURVES
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0
TJ = 25°C
VGS = 0 V
Ciss
Coss
Crss
5 10 15 20 25
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
30
1000
VDD = 15 V
ID = 15 A
VGS = 10 V
100
10
tf
td(off)
tr
td(on)
1
1
1000
10
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
100
10 ms
10 100 ms
1 ms
1 0 V < VGS < 10 V
Single Pulse
TC = 25°C
0.1 RDS(on) LIMIT
THERMAL LIMIT
0.01
0.01
PACKAGE LIMIT
0.1 1
10 ms
dc
10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10
9 QT
8
7
6
5 Qgs
4
Qgd
3 ID = 30 A
2 TJ = 25°C
1
VDD = 15 V
VGS = 10 A
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage vs. Total Charge
30
VGS = 0 V
25
20
TJ = 125°C
TJ = 25°C
15
10
5
0
0.4 0.5 0.6 0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
25
ID = 19 A
50 75 100 125 150 175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
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