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PDF NVD4815N Data sheet ( Hoja de datos )
| Número de pieza | NVD4815N | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NTD4815N, NVD4815N
Power MOSFET
30 V, 35 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
• High Side Switching
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current RqJA
(Note 1)
Power Dissipation
RqJA (Note 1)
Continuous Drain
Current RqJA
(Note 2)
Power Dissipation
RqJA (Note 2)
Steady
State
Continuous Drain
Current RqJC
(Note 1)
Power Dissipation
RqJC (Note 1)
Pulsed Drain
Current
tp=10ms
TA = 25°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
TC = 25°C
TA = 25°C
VDSS
VGS
ID
PD
ID
PD
ID
PD
IDM
30
±20
8.5
6.5
1.92
6.9
5.3
1.26
35
27
32.6
87
V
V
A
W
A
W
A
W
A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
IDmaxPkg
TJ,
TSTG
IS
dV/dt
35
−55 to
+175
27
6
A
°C
A
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (VDD = 24 V, VGS = 10 V,
IL = 11 Apk, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
EAS
60.5 mJ
TL 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 8
1
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
15 mW @ 10 V
25 mW @ 4.5 V
D
ID MAX
35 A
N−Channel
G
S
4
4
12
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
1 23
3 IPAK
CASE 369AC
(Straight Lead)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
A = Assembly Location*
Y = Year
WW = Work Week
4815N = Device Code
G = Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Publication Order Number:
NTD4815N/D
1 page  
NTD4815N, NVD4815N
TYPICAL PERFORMANCE CURVES
1500
1400
1300
VDS = 0 V VGS = 0 V
TJ = 25°C
1200
1100 Ciss
1000
900
800 Ciss
700
600
500 Crss
400
300
200 Coss
100
0
Crss
10 5 0 5 10 15 20 25 30
VGS
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
6 16
5 VDS
4 Q1
QT
Q2
14
12
VGS
10
38
6
2
4
1
ID = 30 A 2
0 TJ = 25°C 0
0 1 2 3 4 5 67
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
1000
100 tr
VDD = 15 V
ID = 30 A
VGS = 11.5 V
td(off)
10
td(on)
tf
1
1 10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
30
VGS = 0 V
25 TJ = 25°C
20
15
10
5
0
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
1000
100
10 ms
10
1
0.1
0.1
100 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1 ms
10 ms
dc
1 10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
70
ID = 11 A
60
50
40
30
20
10
0
25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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| PDF Descargar | [ Datasheet NVD4815N.PDF ] | |
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