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PDF NTLJD3181PZ Data sheet ( Hoja de datos )
| Número de pieza | NTLJD3181PZ | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTLJD3181PZ
Power MOSFET
−20 V, −4.0 A, mCoolt Dual P−Channel,
ESD, 2x2 mm WDFN Package
Features
• WDFN 2x2 mm Package with Exposed Drain Pads for Excellent
Thermal Conduction
• Lowest RDS(on) Solution in 2x2 mm Package
• Footprint Same as SC−88 Package
• Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
• ESD Protected
• This is a Pb−Free Device
Applications
• Optimized for Battery and Load Management Applications in
Portable Equipment
• Li−Ion Battery Charging and Protection Circuits
• High Side Load Switch
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Steady
State
Power Dissipation
(Note 1)
t≤5s
Steady
State
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
t≤5s
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 85°C
TA = 25°C
VDSS
VGS
ID
PD
ID
PD
−20
±8.0
−3.2
−2.3
−4.0
1.5
2.3
−2.2
−1.6
0.71
V
V
A
W
A
W
Pulsed Drain Current
tp = 10 ms
IDM
Operating Junction and Storage Temperature TJ, TSTG
−16
−55 to
150
A
°C
Source Current (Body Diode) (Note 2)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
IS
−1.0
A
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
of 30 mm2, 2 oz Cu.
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 0
1
http://onsemi.com
V(BR)DSS
−20 V
RDS(on) MAX
100 mW @ −4.5 V
144 mW @ −2.5 V
200 mW @ −1.8 V
ID MAX (Note 1)
−4.0 A
D1 D2
G1 G2
S1 S2
P−CHANNEL MOSFET P−CHANNEL MOSFET
D2 D1
MARKING
DIAGRAM
Pin 1
WDFN6
CASE 506AN
1
2
JEMG
6
5
3G 4
JE = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
S1 1
D1
6 D1
G1 2
D2 3
D2
5 G2
4 S2
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NTLJD3181PZTAG WDFN6 3000/Tape & Reel
(Pb−Free)
NTLJD3181PZTBG WDFN6 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTLJD3181PZ/D
1 page  
600
400
200
0
0
NTLJD3181PZ
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
TJ = 25°C
VGS = 0 V
Ciss
5
4
QT
3
2 QGS
QGD
VGS
Coss
5 10 15
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Crss
20
Figure 7. Capacitance Variation
1
ID = −3.8 A
TJ = 25°C
0
0 1 2 3 4 56
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
100
VDD = −5.0 V
ID = −2.0 A
VGS = −4.5 V
10
td(off)
tf
tr
td(on)
2
VGS = 0 V
TJ = 25°C
1.5
1
0.5
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
100
0
0 0.2 0.4 0.6 0.8 1.0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
10 100 ms
1 ms
1
VGS = 20 V
SINGLE PULSE
0.1 TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
0.01
0.1
PACKAGE LIMIT
1
10 ms
dc
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
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