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PDF SAMG51N Data sheet ( Hoja de datos )
| Número de pieza | SAMG51N | |
| Descripción | SMART ARM-based Flash MCU | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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SAM G51G / SAM G51N
Atmel | SMART ARM-based Flash MCU
DATASHEET
Description
The Atmel® | SMART™ SAM G51 series is a member of a family of Flash
microcontrollers based on the high-performance 32-bit ARM® Cortex®-M4 RISC
processor with Floating Point Unit. It operates at a maximum speed of 48 MHz
and features up to 256 Kbytes of Flash and up to 64 Kbytes of SRAM. The
peripheral set includes one USART, two UARTs, two I2C-bus interfaces (TWI),
one high-speed TWI, up to two SPIs, one three-channel general-purpose 16-bit
timer (TC), one RTT and one 8-channel 12-bit ADC.
The Atmel | SMART SAM G51 devices have two software-selectable low-power
modes: Sleep and Wait. In Sleep mode, the processor is stopped while all other
functions can be kept running. In Wait mode, all clocks and functions are stopped.
The Event System allows peripherals to receive, react to and send events in
Active and Sleep modes without processor intervention.
A general-purpose microcontroller with the best ratio in terms of reduced power
consumption, processing power and peripheral set, the SAM G51 series sustains
a wide range of applications including consumer, industrial control, and PC
peripherals.
The device operates from 1.7V to 2.0V and is available in a 49-ball WLCSP
package and a 100-lead LQFP package.
Atmel-11209D-ATARM-SAM-G51G-SAMG-51N-Datasheet_19-Nov-14
1 page  
2. SAM G51 Block Diagram
Figure 2-1. SAM G51 Block Diagram
TST
PCK[2:0]
WKUP[15:0]
XIN
XOUT
XIN32
XOUT32
ERASE
VDDIO
VDDCORE
NRST
PLL
RC OSC
8/16/24 MHz
Power
Management
Controller
3–20 MHz
Oscillator
Supply
Controller
Tamper Detection
32K OSC
32K RC
Power-on
Reset
8 General-purpose
Backup Registers
Real-time
Clock
Real-time
Timer
Watchdog
Timer
Reset
Controller
Supply
Monitor
PIOA/PIOB
System Controller
JTAG and Serial Wire
In-Circuit Emulator
Cortex-M4 Processor
fMAX 48 MHz
DSP
MPU
NVIC
24-bit SysTick
Counter
FPU
I/D S
MM
3-layer AHB Bus Matrix
fMAX 48 MHz
SM
S
S
S
AHB/APB
Bridge
PDC
Voltage
Regulator
Flash
Unique
Identifier
User
Signature
Flash
256 Kbytes
SRAM
64 Kbytes
ROM(1)
8 Kbytes
SCK
TXD
RXD
RTS
CTS
URXD[1:0]
UTXD[1:0]
PDC
USART
PDC
2 x UART
AD[7:0]
ADTRG
VDDIO
PDC
12-bit ADC
Event
System
Note: 1. The ROM is reserved for future use.
PDC
SPI
PDC
3 x TWI
PDC Timer Counter A
TC[0..2]
NPCS0
NPCS1
MISO
MOSI
SPCK
TWCK[2:0]
TWD[2:0]
TCLK[2:0]
TIOA[2:0]
TIOB[2:0]
SAM G51G / SAM G51N [DATASHEET]
Atmel-11209D-ATARM-SAM-G51G-SAMG-51N-Datasheet_19-Nov-14
5
5 Page 
5.4 Functional Modes
5.4.1
Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLL. The power management controller can be used to adapt the frequency and to disable the
peripheral clocks.
5.4.2
Wait Mode
The purpose of Wait mode is to achieve very low power consumption while maintaining the entire device in a
powered state for a wake-up time of less than 5 µs. The wake-up time is achieved while the system is running from
the internal SRAM. The function allowing to enter and exit the Wait mode linked and executed in the internal
SRAM. If the wake-up function is executed in internal Flash, the wake-up time is 70 µs (for C code running in
Flash, the number of wait states must be 0).
The current consumption in Wait mode is typically less than 10 µA (total current consumption). The clocks of the
core, the peripherals and memories are stopped. However, power supplies are still maintained, thus allowing
memory retention, CPU context saving and fast start-up. Wait mode is entered by setting the WAITMODE bit to 1
in the CKGR_MOR in conjunction with FLPM = 0 or FLPM = 1 bits of the PMC_FSMR. or by the Wait for Event
(WFE) instruction.
Note:
The WFE instruction can add complexity in application state machines. This is because the WFE instruction goes
along with an event flag of the Cortex processor (cannot be managed by the software application). The event flag can
be set by interrupts, a debug event or an event signal from another processor. Since an interrupt may take place just
before the execution of WFE, WFE takes into account events that happened in the past. As a result, WFE prevents the
device from entering Wait mode if an interrupt event has occurred. To work around this complexity, the WAITMODE bit
in the PMC Clock Generator Main Oscillator Register of the Power Management Controller (PMC) can be used.
The Cortex-M4 processor is able to handle external or internal events in order to wake up the core. This is done by
configuring the external lines WKUP0–15 as fast start-up wake-up pins (refer to Section 5.5 “Fast Start-up”) or the
RTC, RTT alarms for internal events.
To enter Wait mode with WAITMODE bit:
Select the 8/16/24 MHz fast RC oscillator as Main Clock. If 24 MHz is selected and the C code runs on the
SRAM, wake-up time is less than 5 µs.
Set the FLPM field in the PMC Fast Start-up Mode Register (PMC_FSMR).
Set Flash Wait State to 0.
Set the WAITMODE bit = 1 in PMC Main Oscillator Register (CKGR_MOR).
Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR).
To enter Wait mode with WFE:
Select the 8/16/24 MHz fast RC oscillator as Main Clock. If 24 MHz is selected and the C code runs on the
SRAM, wake-up time is less than 5 µs.
Set the FLPM field in the PMC Fast Start-up Mode Register (PMC_FSMR).
Set Flash Wait State to 0.
Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR).
Execute the Wait-For-Event (WFE) instruction of the processor.
In both cases, depending on the value of the field Flash Low Power Mode (FLPM), the Flash enters three different
modes:
FLPM = 0 in stand-by mode (Low power consumption)
FLPM = 1 in deep power-down mode (Extra-low power consumption)
FLPM = 2 in idle mode. Memory ready for read access.
SAM G51G / SAM G51N [DATASHEET]
Atmel-11209D-ATARM-SAM-G51G-SAMG-51N-Datasheet_19-Nov-14
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAMG51N.PDF ] | |
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