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PDF HMC832 Data sheet ( Hoja de datos )
| Número de pieza | HMC832 | |
| Descripción | Fractional-N PLL | |
| Fabricantes | Analog Devices | |
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Data Sheet
Fractional-N PLL with Integrated VCO
25 MHz to 3000 MHz
HMC832
FEATURES
RF bandwidth:
25 MHz to 3000 MHz
3.3 V supply
Maximum phase detector rate: 100 MHz
Ultralow phase noise
−110 dBc/Hz in band, typical
Fractional figure of merit (FOM): −226 dBc/Hz
24-bit step size, resolution 3 Hz typical
Exact frequency mode with 0 Hz frequency error
Fast frequency hopping
40-lead 6 mm × 6 mm SMT package: 36 mm2
APPLICATIONS
Cellular infrastructure
Microwave radio
WiMax, WiFi
Communications test equipment
CATV equipment
DDS replacement
Military
Tunable reference source for spurious-free performance
GENERAL DESCRIPTION
The HMC832 is a 3.3 V, high performance, wideband, frac-
tional-N, phase-locked loop (PLL) that features an integrated
voltage controlled oscillator (VCO) with a fundamental
frequency of 1500 MHz to 3000 MHz, and an integrated VCO
output divider (divide by 1/2/4/6/…60/62), that enables the
HMC832 to generate continuous frequencies from 25 MHz to
3000 MHz. The integrated phase detector (PD) and delta-sigma
(Δ-Σ) modulator, capable of operating at up to 100 MHz, permit
wider loop bandwidths and faster frequency tuning with
excellent spectral performance.
Industry leading phase noise and spurious performance, across
all frequencies, enable the HMC832 to minimize blocker effects,
and to improve receiver sensitivity and transmitter spectral
purity. A low noise floor (−160 dBc/Hz) eliminates any contri-
bution to modulator/mixer noise floor in transmitter applications.
FUNCTIONAL BLOCK DIAGRAM
LD/SDO SCK SDI
HMC832
LOCK
DETECT
CONTROL
MODULATOR CAL
SPI
PROGRAMMING
INTERFACE
EN
EN
÷1, 2, 4, 6, ...62
SEN
RF_P
RF_N
÷N
CP CP PFD
÷R
VCO
VTUNE
XREFP
Figure 1.
The HMC832 is footprint-compatible to the market leading
HMC830 PLL with integrated VCO. It features 3.3 V supply and
an innovative programmable performance technology that enables
the HMC832 to tailor current consumption and corresponding
noise floor performance to individual applications by selecting
either a low current consumption mode or a high performance
mode for an improved noise floor performance.
Additional features of the HMC832 include 12 dB of RF output
gain control in 1 dB steps; output mute function to automatically
mute the output during frequency changes when the device is
not locked; selectable output return loss; programmable
differential or single-ended outputs, with the ability to select
either output in single-ended mode; and a Δ-Σ modulator exact
frequency mode that enables users to generate output frequencies
with 0 Hz frequency error.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
HMC832
Parameter
VCO CHARACTERISTICS
VCO Tuning Sensitivity
2800 MHz
2400 MHz
2000 MHz
1600 MHz
VCO Supply Pushing
Test Conditions/Comments
Measured with 1.5 V on VTUNE; see Figure 29
Measured with 1.5 V on VTUNE; see Figure 29
Measured with 1.5 V on VTUNE; see Figure 29
Measured with 1.5 V on VTUNE; see Figure 29
Measured with 1.5 V on VTUNE
Min Typ
24.6
25.8
25.2
24.3
2.8
Max Unit
MHz/V
MHz/V
MHz/V
MHz/V
MHz/V
1 Measured with 100 Ω external termination. See Reference Input Stage section for more details.
2 Slew rate of ≥0.5 ns/V is recommended, see Reference Input Stage section for more details. Frequency is guaranteed across process voltage and temperature from
−40°C to +85°C.
3 This maximum PD frequency can only be achieved if the minimum N value is respected. For example, in the case of fractional mode, the maximum PD frequency =
fVCO/20 or 100 MHz, whichever is less.
4 For detailed current consumption information, refer to Figure 33 and Figure 36.
5 Gain setting = 6 (VCO_REG 0x07[3:0] = 6d) in high performance mode (VCO_REG 0x03[1:0] = 3d).
TIMING SPECIFICATIONS
SPI Write Timing Characteristics
AVDD = DVDD = 3 V, AGND = DGND = 0 V.
Table 2. SPI Write Timing Characteristics, See Figure 47
Parameter
Test Conditions/Comments
Min Typ Max Unit
t1
SDI setup time to SCLK rising edge
3
ns
t2
SCLK rising edge to SDI hold time
3
ns
t3 SEN low duration
10
ns
t4 SEN high duration
10
ns
t5
SCLK 32nd rising edge to SEN rising edge
10
ns
t6 Recovery time 20 ns
Maximum serial port clock speed
50 MHz
Table 3. SPI Read Timing Characteristics, See Figure 48
Parameter
Test Conditions/Comments
t1 SDI setup time to SCK rising edge
t2 SCK rising edge to SDI hold time
t3 SEN low duration
t4 SEN high duration
t5 SCK rising edge to SDO time
t6 Recovery time
t7 SCK 32nd rising edge to SEN rising edge
Min Typ
Max Unit
3 ns
3 ns
10 ns
10 ns
8.2 ns + 0.2 ns/pF
ns
10 ns
10 ns
Rev. A | Page 5 of 48
5 Page 
Data Sheet
–50 –40°C
+27°C
–55 +85°C
0.4460
–60 0.1410
–65
–70 0.0447
–75
–80 0.0141
–85
PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz
–90
100 1000
OUTPUT FREQUENCY (MHz)
0.0045
Figure 21. Single Sideband Integrated Phase Noise, High Performance Mode,
Loop Filter Type 2 (See Table 12)
15
RETURN LOSS (VCO_REG0x03[5] = 0)
RETURN LOSS (VCO_REG0x03[5] = 1)
10
HIGH PERFORMANCE MODE
(VCO_REG0x03[1:0] = 3d)
5
0
–5
LOW CURRENT MODE
(VCO_REG0x03[1:0] = 1d)
–10
PHASE NOISE INTEGRATED FROM 10kHz TO 20MHz
–15
25 100
1000
3000
FREQUENCY (MHz)
Figure 22. Typical Single-Ended Output Power vs. Frequency (Mid Gain
Setting 6)
10
–40°C
+27°C
8 +85°C
6
4
2
0
–2
–4
–6
0 2 4 6 8 10
GAIN SETTING
Figure 23. Typical RF Output Power at 2 GHz (Single-Ended) vs. Temperature
HMC832
–200
–210
–220
–230
TYP FOM VS OFFSET
FOM 1/f NOISE
FOM FLOOR
–240
100
1k 10k 100k
OFFSET (Hz)
Figure 24. Figure of Merit
1M
20
15
GAIN SETTING = 11
10 (VCO_REG0x07[3:0] = 11d)
5 GAIN SETTING = 5
(VCO_REG0x07[3:0] = 5d)
0 GAIN SETTING = 0
(VCO_REG0x07[3:0] = 0d)
–5
–10
–15
–20
25
HIGH PERFORMANCE MODE
LOW CURRENT MODE
100
FREQUENCY (MHz)
1000
3000
Figure 25. Typical Output Power vs. Frequency and Gain (Single-Ended)
0
RETURN LOSS 0 (VCO_REG0x03[5] = 0)
–5
RETURN LOSS 1 (VCO_REG0x03[5] = 1)
–10
–15
–20
–25
–30
25
100 1000
OUTPUT FREQUENCY (MHz)
Figure 26. RF Output Return Loss
8000
Rev. A | Page 11 of 48
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HMC832.PDF ] | |
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