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PDF NCV8878 Data sheet ( Hoja de datos )
| Número de pieza | NCV8878 | |
| Descripción | Automotive Grade Start-Stop Non-Synchronous Boost Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCV8878
Automotive Grade
Start-Stop Non-Synchronous
Boost Controller
The NCV8878 is a Non-Synchronous Boost controller designed to
supply a minimum output voltage during Start-Stop vehicle operation
battery voltage sags. The controller drives an external N-channel
MOSFET. The device uses peak current mode control with internal
slope compensation. The IC incorporates an internal regulator that
supplies charge to the gate driver.
Protection features include, cycle-by-cycle current limiting and
thermal shutdown.
Additional features include low quiescent current sleep mode
operation. The NCV8878 is enabled when the supply voltage drops
below the wake up threshold. Boost Operation is initiated when the
supply voltage drops below the regulation set point.
Features
• Automatic Enable Below Wake Up Threshold Voltage (Factory
Programmable)
• Status Pin Diagnostic Function
• Override Disable Function
• Boost Mode Operation at Regulation Set Point
• $2% Output Accuracy Over Temperature Range
• Peak Current Mode Control with Internal Slope Compensation
• Wide Input Voltage Range of 2 V to 40 V, 45 V Load Dump
• Low Quiescent Current in Sleep Mode (<12 mA Typical)
• Cycle−by−Cycle Current Limit Protection
• Hiccup−Mode Overcurrent Protection (OCP)
• Thermal Shutdown (TSD)
• This is a Pb−Free Device
Typical Applications
• Applications Requiring Regulated Voltage through Cranking and
Start−Stop Operation
www.onsemi.com
8
1
SOIC−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
8878xx
ALYW
G
1
8878xx = Specific Device Code
xx = 01 or 11
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN CONNECTIONS
STATUS 1
ISNS 2
GND 3
GDRV 4
8 DISB
7 VC
6 VOUT
5 VDRV
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV887801D1R2G SOIC−8 2500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 2
1
Publication Order Number:
NCV8878/D
1 page  
NCV8878
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.6 V < VOUT < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min Typ Max Unit
GATE DRIVER
Sinking Current
Driving Voltage Dropout (Note 2)
Driving Voltage Source Current
Backdrive Diode Voltage Drop
Driving Voltage
Pull−down Resistance
Isink
Vdrv,do
Idrv
Vd,bd
VDRV
VGDRV ≥ 2 V
VOUT − VDRV, IvDRV = 25 mA
VOUT − VDRV = 1 V
VDRV – VOUT, Id,bd = 5 mA
IVDRV = 0.1 − 25 mA
480 600 − mA
− 0.3 0.6 V
35 45
− mA
− − 0.7 V
5.8 6.0 6.2
V
− 21 − kW
UVLO
Undervoltage Lock−out,
Threshold Voltage
Vuvlo,fall
VOUT falling
3.40 3.59 3.80
V
Undervoltage Lock−out
THERMAL SHUTDOWN
Vuvlo, rise VOUT rising
3.90 4.05 4.20
V
Thermal Shutdown Threshold (Note Tsd TJ rising
2)
160 170 180
°C
Thermal Shutdown Hysteresis (Note
2)
Tsd,hys
TJ falling
10 15 20 °C
Thermal Shutdown Delay (Note 2)
VOLTAGE REGULATION
tsd,dly
From TJ > Tsd to stop switching
− − 100 ns
Voltage Regulation
Threshold IC Enable
Threshold IC Disable
Threshold IC Enable – Voltage Reg-
ulation
VOUT,reg
VOUT descending
VOUT ascending
NCV887801 6.66 6.80 6.94
NCV887801 7.10 7.30 7.50
NCV887801 7.55 7.75 7.95
NCV887801 0.32
0.5
−
V
V
V
V
Threshold IC Disable – Threshold
IC Enable
NCV887801
−
0.4
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Not tested in production. Limits are guaranteed by design.
www.onsemi.com
5
5 Page 
NCV8878
9. Design Notes
• VOUT serves a dual purpose (feedback and IC power).
The VDRV circuit has a current pulse power draw
resulting in current flow from the output sense location
to the IC. Trace ESL will cause voltage ripple to
develop at IC pin VOUT which could affect
performance.
♦ Use a 1 mF IC VOUT pin decoupling capacitor close
to IC in addition to the VDRV decoupling capacitor.
• Classic feedback loop measurements are not possible
(VOUT pin serves a dual purpose as a feedback path
and IC power). Feedback loop computer modeling
recommended.
♦ A step load test for stability verification is
recommended.
• Compensation ground must be dedicated and connected
directly to IC ground.
♦ Do not use vias. Use a dedicated ground trace.
• IC ground & current sense resistor ground sense point
must be located on the same side of PCB.
♦ Vias introduce sufficient ESR/ESL voltage drop
which can degrade the accuracy of the current
feedback signal amplitude (signal bounce) and
should be avoided.
• Star ground should be located at IC ground pad.
♦ This is the location for connecting the compensation
and current sense grounds.
• The IC architecture has a leading edge ISNS blanking
circuit. In some instances, current pulse leading edge
current spike RC filter may be required.
♦ If required, 330 pF + 250 W are a recommended
evaluation starting point.
• RDAMPING (optional)
♦ The IC-VOUT pin may be located a few cm from
the output voltage sensing point. Parasitic
inductance from the feedback trace (roughly
5 nH/cm) results in the requirement for a decoupling
capacitor (Cdecoupling = 1 mF recommended) next to
the IC-VOUT pin to support the VDRV charging
pulses. The IC-VDRV energy is replenished from
current pulses by an internal linear regulator whose
charging frequency corresponds to that of the IC
oscillator (phase lag may occur; some charging
pulses may occasionally be skipped depending on
the state of the VDRV voltage). The trace’s parasitic
inductance can introduce a low amplitude damped
voltage oscillation between the IC-VOUT and the
output voltage sense location which may result in
minor frequency jitter.
♦ If the measured frequency jitter is objectionable, it
may be attenuated by placing a series damping
resistor (Rdamp) in the feedback path between the
output voltage sense and IC-VOUT. The resulting
filter introduced by Rdamp introduces a high
frequency pole in the feedback loop path. The RC
filter 3 dB pole frequency must be chosen at a
minimum of 1 decade above the design’s feedback
loop cross-over frequency (at minimum power
supply input voltage where the worst case phase
margin will occur) to avoid deteriorating the
feedback loop cross-over frequency phase margin.
♦ The average operating current demand from the IC
is dominated by the MOSFET gate drive power
energy consumption (IVDRV = Qg(tot)_6V x fosc).
The IVDRV x Rdamp voltage drop results in a
corresponding increase in power supply regulation
voltage. Rdamp is typically 0.68 W, so the resulting
increase in output voltage regulation will be minimal
(10-30 mV may be typical).
10. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC−VC signal if R2 is of similar order of magnitude as RESD.
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type−I compensation is not possible due to the presence
of RESD. The Figure 14 compensation network corresponds
to a Type−II network in series with RESD. The resulting
control−output transfer function is an accurate mathematical
model of the IC in a boost converter topology. The model
does have limitations and a more accurate SPICE model
should be considered for a more detailed analysis:
• The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
• The efficiency term h should be a reasonable operating
condition estimate.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet NCV8878.PDF ] | |
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