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NCP51145 PDF даташит

Спецификация NCP51145 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «Termination Regulator».

Детали детали

Номер произв NCP51145
Описание Termination Regulator
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NCP51145 Даташит, Описание, Даташиты
NCP51145
DDR 1.8 Amp Source / Sink
VTT Termination Regulator
The NCP51145 is a linear regulator designed to supply a regulated
VTT termination voltage for DDR−II, DDR−III, LPDDR−III and
DDR−IV memory applications. The regulator is capable of actively
sourcing and sinking ±1.8 A peak currents while regulating an output
voltage to within ±20 mV. The output termination voltage is regulated
to track VDDQ / 2 by two external voltage divider resistors connected
to the PVCC, GND, and VREF pins.
The NCP51145 incorporates a high−speed differential amplifier to
provide ultra−fast response to line and load transients. Other features
include source/sink current limiting, soft−start and on−chip thermal
shutdown protection.
Features
For DDR VTT Applications, Source/Sink Currents:
Supports DDR−II to ±1.8 A, DDR−III to ±1.5 A
Supports LPDDR−III and DDR−IV to ±1.2 A
Stable Using Ceramic−Only (Very Low ESR) Capacitors
Integrated Power MOSFETs
High Accuracy VTT Output at Full−Load
Fast Transient Response
Built−in Soft−Start
Shutdown for Standby or Suspend Mode
Integrated Thermal and Current−Limit Protection
VTT Remote Sense Available in the DFN8 2x2mm Package
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
DDR−II / DR−III / DDR−IV SDRAM Termination Voltage
Motherboard, Notebook, and VGA Card Memory Termination
Set Top Box, Digital TV, Printers
Low Power DDR−3LP
www.onsemi.com
MARKING
DIAGRAMS
8
8
1
SOIC−8 EP
D SUFFIX
CASE 751BU
51145
AYWWG
G
1
DFN8
MN SUFFIX
CASE 506AA
1
XXMG
G
1
51145
XX
M
A
Y
WW
G
= Specific Device Code
= Specific Device Code
= Date Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
1 81
8
PVCC
NC PVCC
VCC
GND
NC
VREF
VCC
VTT SOIC−8 EP NC
VTT
NC
GND
NC
VTTS
VREF
DFN8 2x2, 0.5P
(Top Views)
ORDERING INFORMATION
Device
Package
Shipping
NCP51145PDR2G SOIC−8 2500 / Tape &
(Pb−Free)
Reel
NCP51145MNTAG DFN−8 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 2
1
Publication Order Number:
NCP51145/D









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NCP51145 Даташит, Описание, Даташиты
NCP51145
PVCC = 1.0 to 5.5 V*
R2
100k
C2
NCP51145
SO8−EP Package
1
PVCC
6
VCC
2
GND
C3
R4 5 V
2.2
Enable
R1
100k
3
VREF
C1
4
VTT
VTT = 0.6 to 2.5 V*
C4
R3
EP
C1 = 1 to 100 nF Ceramic
C2 = 10 mF Ceramic
C3 = 1 mF
C4 = 10 mF Ceramic
R3 = Optional VTT Discharge Resistor
N−Ch MOSFET = Optional Enable / Disable
Figure 1. Application Diagram
*For DDR2: PVCC = 1.8 V, VTT = 0.9 V
DDR3: PVCC = 1.5 V, VTT = 0.75 V
DDR4: PVCC = 1.2 V, VTT = 0.60 V
PIN FUNCTION DESCRIPTION
Pin No.
SO8−EP
Pin No.
DFN8
Pin Name
1 1 PVCC
2 4 GND
3 5 VREF
4 2 VTT
5, 7, 8
6
3, 7
8
NC
VCC
− 6 VTTS
EP EP EPAD
Description
Input voltage which supplies current to the output pin. CIN ^ ½ S COUT
Common Ground
Buffered reference voltage input equal to ½ of VDDQ and active low shutdown pin. An
external resistor divider dividing down the PVCC voltage creates the regulated output
voltage. Pulling the pin to ground (0.15 V maximum) turns the device off.
Regulator output voltage capable of sourcing and sinking current while regulating the
output rail. COUT = 10 mF Ceramic, or greater
True No Connect
The VCC pin is a 5 V input pin that provides internal bias to the controller. PVCC should
always be kept lower or equal to VCC.
VTT Sense
Pad for thermal connection. The exposed pad must be connected to the ground plane
using multiple vias for maximum power dissipation performance.
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NCP51145 Даташит, Описание, Даташиты
NCP51145
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Supply Voltage Range (Vcc w PVCC) (Note 1)
PVCC,
VCC
−0.3 to 6
V
Output Voltage Range
Reference Input Range
Maximum Junction Temperature
Storage Temperature Range
VTT
VREF
TJ(max)
TSTG
−0.3 to 6
−0.3 to 6
150
−65 to 150
V
V
°C
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2
kV
ESD Capability, Machine Model (Note 2)
ESDMM
200
V
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 3)
TSLD
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
THERMAL CHARACTERISTICS
Rating
Symbol
Thermal Characteristics, SO8−EP (Note 4)
Thermal Resistance, Junction−to−Air (Note 5)
Thermal Reference, Junction−to−Lead2 (Note 5)
RqJA
RYJL
4. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
5. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
Value
82
TBD
Unit
°C/W
OPERATING RANGES (Note 6)
Rating
Symbol
Min
Max Unit
Input Voltage
PVCC
1.0
5.5 V
Bias Supply Voltage
VCC 4.75
5.25 V
Ambient Temperature
TA −40
85 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
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Номер в каталогеОписаниеПроизводители
NCP51145Termination RegulatorON Semiconductor
ON Semiconductor

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