NCY9100 Datasheet PDF - ON Semiconductor
| Part Number | NCY9100 | |
| Description | Compandor | |
| Manufacturers | ON Semiconductor | |
| Logo |  |
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NCY9100
Compandor
The NCY9100 is a versatile low cost dual gain control circuit in
which either channel may be used as a dynamic range compressor or
expandor. Each channel has a full−wave rectifier to detect the average
value of the signal, a linerarized temperature−compensated variable
gain cell, and an operational amplifier.
The NCY9100 is well suited for use in cellular radio and radio
communications systems, modems, telephone, and satellite
broadcast/receive audio systems.
Features
• Complete Compressor and Expandor in one IChip
• Temperature Compensated
• Greater than 110 dB Dynamic Range
• Operates Down to 6.0 VDC
• System Levels Adjustable with External Components
• Distortion may be Trimmed Out
• Dynamic Noise Reduction Systems
• Voltage Controlled Amplifier
• This is a Pb−Free Device
Applications
• Cellular Radio
• High Level Limiter
• Low Level Expandor − Noise Gate
• Dynamic Filters
• CD Player
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1
SOIC−16 WB
D SUFFIX
CASE 751G
A
WL
YY
WW
G
MARKING
DIAGRAMS
16
NCY9100
AWLYYWWG
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
RECT CAP 1 1
RECT IN 1 2
DG CELL IN 1 3
GND 4
INV. IN 1 5
RES. R3 1 6
OUTPUT 1 7
THD TRIM 1 8
16 RECT CAP 2
15 RECT IN 2
14 DG CELL IN 2
13 VCC
12 INV. IN 2
11 RES. R3 2
10 OUTPUT 2
9 THD TRIM 2
TOP VIEW
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 0
1
Publication Order Number:
NCY9100/D
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NCY9100
INTRODUCTION
Much interest has been expressed in high performance
electronic gain control circuits. For non−critical
applications, an integrated circuit operational
transconductance amplifier can be used, but when
high−performance is required, one has to resort to complex
discrete circuitry with many expensive, well−matched
components. This paper describes an inexpensive integrated
circuit, the NCY9100 Compandor, which offers a pair of
high performance gain control circuits featuring low
distortion (<0.1%), high signal−to−noise ratio (90 dB), and
wide dynamic range (110 dB).
Circuit Background
The NCY9100 Compandor was originally designed to
satisfy the requirements of the telephone system. When
several telephone channels are multiplexed onto a common
line, the resulting signal−to−noise ratio is poor and
companding is used to allow a wider dynamic range to be
passed through the channel. Figure 4 graphically shows
what a compandor can do for the signal−to−noise ratio of a
restricted dynamic range channel. The input level range of
+20 to −80 dB is shown undergoing a 2−to−1 compression
where a 2.0 dB input level change is compressed into a
1.0 dB output level change by the compressor. The original
100 dB of dynamic range is thus compressed to a 50 dB
range for transmission through a restricted dynamic range
channel. A complementary expansion on the receiving end
restores the original signal levels and reduces the channel
noise by as much as 45 dB.
The significant circuits in a compressor or expander are
the rectifier and the gain control element. The phone system
requires a simple full−wave averaging rectifier with good
accuracy, since the rectifier accuracy determines the (input)
output level tracking accuracy. The gain cell determines the
distortion and noise characteristics, and the phone system
specifications here are very loose. These specs could have
been met with a simple Operational Transconductance
Multiplier, or OTA, but the gain of an OTA is proportional
to temperature and this is very undesirable. Therefore, a
linearized transconductance multiplier was designed which
is insensitive to temperature and offers low noise and low
distortion performance. These features make the circuit
useful in audio and data systems as well as in
telecommunications systems.
Basic Hook−up and Operation
Figure 5 shows the block diagram of one half of the chip,
(there are two identical channels on the IC). The full−wave
averaging rectifier provides a gain control current, IG, for the
variable gain (DG) cell. The output of the DG cell is a current
which is fed to the summing node of the operational
amplifier. Resistors are provided to establish circuit gain and
set the output DC bias.
The circuit is intended for use in single power supply
systems, so the internal summing nodes must be biased at
some voltage above ground. An internal band gap voltage
reference provides a very stable, low noise 1.8 V reference
denoted VREF. The non−inverting input of the op amp is tied
to VREF, and the summing nodes of the rectifier and DG cell
(located at the right of R1 and R2) have the same potential.
The THD trim pin is also at the VREF potential.
INPUT
LEVEL
+20
0dB
OUTPUT
LEVEL
−20
0dB
−40
NOISE
−80
−40
−80
Figure 4. Restricted Dynamic Range Channel
GIN
3,14
RECTIN
THD TRIM
R3 INVIN
8,9
R3
6,11 5,12
R2
20kW
R1
20kW
DG
IG
R4
30kW
−
VREF +
1.8V
OUTPUT
7,10
2,15 10kW
1,16
VCC PIN 13
GND PIN 4
CRECT
Figure 5. Chip Block Diagram (1 of 2 Channels)
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| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ NCY9100.PDF Datasheet ] | |
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