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PDF NCP1602 Data sheet ( Hoja de datos )
| Número de pieza | NCP1602 | |
| Descripción | High-Efficiency Power Factor Controller | |
| Fabricantes | ON Semiconductor | |
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NCP1602
Enhanced, High-Efficiency
Power Factor Controller
The 6−pin PFC controller NCP1602 is designed to drive PFC boost
stages. It is based on an innovative Valley Synchronized Frequency
Fold−back (VSFF) method. In this mode, the circuit classically
operates in Critical conduction Mode (CrM) when Vcontrol voltage
exceeds a programmable value Vctrl,FF. When Vcontrol is below this
preset level Vctrl,FF, the NCP1602 (versions [B**] and [D**]) linearly
decays the frequency down to about 30 kHz until Vcontrol reaches the
SKIP mode threshold. VSFF maximizes the efficiency at both
nominal and light load. In particular, the stand−by losses are reduced
to a minimum. Like in FCCrM controllers, internal circuitry allows
near−unity power factor even when the switching frequency is
reduced. Housed in a TSOP6 package, the circuit also incorporates the
features necessary for robust and compact PFC stages, with few
external components.
www.onsemi.com
TSOP−6
SN SUFFIX
1 CASE 318G
MARKING DIAGRAM
AEA AYWG
G
General Features
• Near−Unity Power Factor
• Two−Level Boost Follower Line Level Dependent (disabled by default)
• Critical Conduction Mode (CrM)
• Valley Synchronized Frequency Fold−back (VSFF): Low Frequency
Operation is Forced at Low Current Levels
• Works With or Without a Transformer w/ ZCD Winding (simple inductor)
1
AEA
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
• On−time Modulation to Maintain a Proper Current Shaping in VSFF Mode
• Skip Mode at Very Low Load Current (versions[ B**] and [D**])
• Fast Line / Load Transient Compensation (Dynamic Response Enhancer)
PIN CONNECTIONS
VCTRL 1
6 FB
• Valley Turn−on
• High Drive Capability: −500 mA / +800 mA
• VCC Range: from 9.5 V to 30 V
• Low Start−up Consumption for:
[**C] & [**D] Versions: Low Vcc Start−up level (10.5 V)
[**A] & [**B] Versions: High Vcc Start−up level (17.0 V)
• Line Range Detection for Reduced Crossover Frequency Spread
• This is a Pb−Free Device
GND 2
CS / ZCD 3
5 VCC
4 DRV
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Safety Features
• Thermal Shutdown
• Non−latching, Over−Voltage Protection
• Second Over−Voltage Protection
• Brown−Out Detection
• Soft−Start for Smooth Start−up Operation ([**C] &
[**D] Versions)
• Over Current Limitation
• Disable Protection if the Feedback Pin is Not Connected
• Low Duty−Cycle Operation if the Bypass Diode is
Shorted
• Open Ground Pin Fault Monitoring
Typical Applications
• PC Power Supplies
• Lighting Ballasts (LED, Fluorescent)
• Flat TV
• All Off Line Appliances Requiring Power Factor
Correction
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 2
1
Publication Order Number:
NCP1602/D
1 page  
NCP1602
Table 6. TYPICAL ELECTRICAL CHARACTERISTICS
(Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol
Rating
Min Typ Max Unit
START−UP AND SUPPLY CIRCUIT
VCC,on
Start−Up Threshold, VCC increasing:
[**C] & [**D] Versions
[**A] & [**B] Versions
9.75
15.80
10.50
17.00
11.25
18.20
V
VCC,off
VCC,hyst
Minimum Operating Voltage, VCC falling
Hysteresis (VCC,on − VCC,off)
[**C] & [**D] Versions
[**A] & [**B] Versions
8.50 9.00 9.50 V
V
0.75 1.50
−
6.00 8.00
−
ICC,start
Maximum Start−Up Current, for VCC lower than 9.4 V, below startup voltage
ICC,op1
Operating Consumption, no switching.
ICC,op2
Operating Consumption, 50−kHz switching, no load on DRV pin
FREQUENCY FOLD−BACK DEAD TIME FOR CONFIGURATIONS L2 = B, E, H @ Km = 2.28
tDT,E,1
Dead−Time, Vctrl = 0.65V w/ E config
tDT,E,2
Dead−Time, Vctrl = 0.75V w/ E config
CrM TO DCM THRESHOLD AND HYSTERESIS
− − 480 mA
− 0.5 1.00 mA
− 2.00 3.00 mA
9.96 13.28 16.60 ms
6.70 8.93 10.80 ms
Vctrl,th,E
Vctrl threshold CrM to DCM mode w/ E config
SKIP CONTROL ([B**] & [D**] Versions)
1.398 1.553 1.708 V
VSKIP−H
VSKIP−L
VSKIP−Hyst
GATE DRIVE
Vctrl pin SKIP Level, Vcontrol rising
Vctrl pin SKIP Level, Vcontrol falling
Vctrl pin SKIP Hysteresis
555 617 678 mV
516 593 665 mV
− 30 − mV
tR
Output voltage rise−time @ CL = 1 nF, 10−90% of output signal
− 30 − ns
tF
Output voltage fall−time @ CL = 1 nF, 10−90% of output signal
− 20 − ns
ROH
Source resistance @ 200 mV under High VCC
− 10 − Ω
ROL
Sink resistance @200 mV above Low VCC
− 7 −Ω
VDRV,low DRV pin level for VCC = VCC,off +200 mV (10−kΩ resistor between DRV and GND) 8.0
−
−V
VDRV,high
DRV pin level at VCC = 30 V (RL = 33 kΩ & CL = 1 nF)
10 12 14 V
REGULATION BLOCK
VREF
Feedback Voltage Reference
VREF2,HL
Feedback Voltage Reference #2 @ High Line
VREF2,LL
Feedback Voltage Reference #2 @ Low Line
IEA Error Amplifier Current Capability, Sinking and Sourcing
GEA Error Amplifier Gain
Vctrl
Vctrl,min
Vctrl,max
VCTRL pin Voltage (Vctrl):
− @ VFB = 2 V (OTA is sourcing 20 mA)
− @ VFB = 3 V (OTA is sinking 20 mA)
Vout,L / VREF2
Ratio (Vout Low Detect Threshold / VREF) (guaranteed by design)
Hout,L / VREF2
Ratio (VoutLow Detect Hysteresis / VREF) (guaranteed by design)
IBOOST
VCTRL pin Source Current when (VOUT Low Detect) is activated
CURRENT SENSE AND ZERO CURRENT DETECTION BLOCKS
2.44 2.50 2.56 V
2.44 2.50 2.56 V
1.56 1.60 1.64 V
15 20 26 mA
110 200 290 mS
− 4.5 − V
− 0.5 − V
− 95.5 − %
− 0.35 − %
147 220 277 mA
VCS(th)
Current Sense Voltage Reference
450 500 550 mV
VCS,OVS(th)
Current Sense Overstress Voltage Reference
675 750 825 mV
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
www.onsemi.com
5
5 Page 
NCP1602
TYPICAL CHARACTERISTICS
2.56
2.54
2.52
2.50
2.48
2.46
2.44
−60 −40 −20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Feedback Voltage Reference (VREF)
vs. Junction Temperature
−16
−17
−18
−19
−20
−21
−22
−23
−24
−60 −40 −20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Error Amplifier Current Capability,
Sinking (IEA2) vs. Junction Temperature
23.6
22.6
21.6
20.6
19.6
18.6
17.6
16.6
15.6
−60 −40 −20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Error Amplifier Current Capability,
Sourcing (IEA1) vs. Junction Temperature
290
270
250
230
210
190
170
150
130
110
−60 −40 −20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Error Amplifier Transconductance
(GEA) vs. Junction Temperature
280
230
180
130
80
−60 −40 −20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Watch Dog Timer Duration (tWDG)
vs. Junction Temperature
1200
1100
1000
900
800
700
600
500
400
−60 −40 −20 0 20 40 60 80 100 120 140
TJ, JUNCTION TEMPERATURE (°C)
Figure 20. Watch Dog Timer Duration in
“OverStress” Situation (tWDG(OS)) vs. Junction
Temperature
www.onsemi.com
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet NCP1602.PDF ] | |
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