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PDF NCP6121 Data sheet ( Hoja de datos )
| Número de pieza | NCP6121 | |
| Descripción | Dual Output 3 Phase +1/0 Phase Controller | |
| Fabricantes | ON Semiconductor | |
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NCP6121
Dual Output 3 Phase +1/0
Phase Controller with
Single SVID Interface for
Desktop and Notebook CPU
Applications
http://onsemi.com
The NCP6121 dual output three plus one phase buck solution is
optimized for Intel VR12 compatible CPUs. The controller combines
true differential voltage sensing, differential inductor DCR current
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for Desktop applications. The
control system is based on Dual−Edge pulse−width modulation
(PWM) combined with DCR current sensing providing the fastest
initial response to dynamic load events and reduced system cost. It
also sheds to single phase during light load operation and can auto
frequency scale in light load while maintaining excellent transient
performance.
Dual high performance operational error amplifiers are provided to
simplify compensation of the system. Patented Dynamic Reference
Injection further simplifies loop compensation by eliminating the need
to compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
MARKING
DIAGRAM
1 52
QFN−52
CASE 485BE
NCP6121
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
Features
• Meets Intel VR12 and IMVP7 Specifications
• Current Mode Dual Edge Modulation for Fastest Initial Response to
Transient Loading
• Dual High Performance Operational Error Amplifier
• Switching Frequency Range of 200 kHz – 1.0 MHz
• One Digital Soft Start Ramp for Both Rails
• Dynamic Reference Injection
• Accurate Total Summing Current Amplifier
• DAC with Droop Feed−forward Injection
• Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
• Phase−to−Phase Dynamic Current Balancing
• “Lossless” DCR Current Sensing for Current Balancing
• Summed Thermally Compensated Inductor Current
Sensing for Droop
• Startup into Pre−Charged Loads While Avoiding False
OVP
• Power Saving Phase Shedding
• Vin Feed Forward Ramp Slope
• Pin Programming for Internal SVID parameters
• Over Voltage Protection (OVP) and Under Voltage
Protection (UVP)
• Over Current Protection (OCP)
• Dual Power Good Output with Internal Delays
• These Devices are Pb−Free and are RoHS Compliant
• True Differential Current Balancing Sense Amplifiers
for Each Phase
• Adaptive Voltage Positioning (AVP)
Applications
• Desktop and Notebook Processors
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 2
1
Publication Order Number:
NCP6121/D
1 page  
NCP6121
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
COMP,COMPA
CSCOMP, CSCOMPA
VSN
DIFFOUT, DIFFOUTA
VR_RDY,VR_RDYA
VCC
ROSC
IOUT, IOUTA Output
VRMP
All Other Pins
**All signals referenced to GND unless noted otherwise.
VMAX
VCC + 0.3 V
VCC + 0.3 V
GND + 300 mV
VCC + 0.3 V
VCC + 0.3 V
6.5 V
VCC + 0.3 V
2.0 V
+25 V
VCC + 0.3V
VMIN
−0.3 V
−0.3 V
GND – 300 mV
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
Unit
V
V
mV
V
V
V
V
V
V
V
THERMAL INFORMATION
Pin Symbol
Thermal Characteristic
QFN Package, (Note 1)
Operating Junction Temperature Range, (Note 2)
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Moisture Sensitivity Level
QFN Package
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
Symbol
RqJA
TJ
TSTG
MSL
Typ
68
−10 to 125
−10 to 100
− 40 to +150
1
Unit
°C/W
°C
°C
°C
NCP6121 ELECTRICAL CHARACTERISTICS Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min Typ Max
ERROR AMPLIFIER
Input Bias Current
@ 1.3 V
−400
400
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
55
Slew Rate
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND, DC Load =
10k to GND
20
Maximum Output Voltage
Minimum Output Voltage
DIFFERENTIAL SUMMING AMPLIFIER
ISOURCE = 2.0 mA
ISINK = 2.0 mA
3.5 −
−−
−
1
Input Bias Current
VSP, VSPA ,VSN, VSNA = 1.3 V −400
−
400
VSP Input Voltage Range
−0.3
−
3.0
VSN Input Voltage Range
−0.3
−
0.3
Unit
nA
dB
MHz
V/ms
V
V
nA
V
V
http://onsemi.com
5
5 Page 
Table 1. VR12 VID CODES
VID7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
NCP6121
VID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
http://onsemi.com
11
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Voltage
(V)
0.49500
0.50000
0.50500
0.51000
0.51500
0.52000
0.52500
0.53000
0.53500
0.54000
0.54500
0.55000
0.55500
0.56000
0.56500
0.57000
0.57500
0.58000
0.58500
0.59000
0.59500
0.60000
0.60500
0.61000
0.61500
0.62000
0.62500
0.63000
0.63500
0.64000
0.64500
0.65000
0.65500
0.66000
0.66500
0.67000
0.67500
0.68000
0.68500
0.69000
0.69500
HEX
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet NCP6121.PDF ] | |
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