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PDF NPIC6C596A Data sheet ( Hoja de datos )
| Número de pieza | NPIC6C596A | |
| Descripción | Power logic 8-bit shift register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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NPIC6C596A
Power logic 8-bit shift register; open-drain outputs
Rev. 1 — 23 October 2013
Product data sheet
1. General description
The NPIC6C596A is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset MR input. A LOW on MR resets both the shift register and storage
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. To provide additional hold time in cascaded
applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the
storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS
transistors designed for use in systems that require moderate load power such as LEDs.
Integrated voltage clamps in the outputs provide protection against inductive transients.
These voltage clamps make the device suitable for power driver applications such as
relays, solenoids and other low-current or medium-voltage loads.
2. Features and benefits
Specified from 40 C to +125 C
Wide supply range 2.3 V to 5.5 V
Low RDSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
Enhanced cascading for multiple stages
All registers cleared with single input
Low power consumption
ESD protection:
HBM JDS-001 Class 2 exceeds 2500 V
CDM JESD22-C101E exceeds 1000 V
1 page  
NXP Semiconductors
NPIC6C596A
Power logic 8-bit shift register; open-drain outputs
6. Pinning information
6.1 Pinning
9&&
'6
4
4
4
4
05
2(
13,&& $
*1'
6+&3
4
4
4
4
67&3
46
DDD
Fig 7. Pin configuration SO16 and TSSOP16
13,&& $
WHUPLQDO
LQGH[DUHD
'6
4
4
4
4
05
6+&3
4
4
4
4
67&3
DDD
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 8. Pin configuration DHVQFN16
6.2 Pin description
Table 2. Pin description
Symbol
VCC
DS
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
MR
OE
Q7S
STCP
SHCP
GND
Pin
1
2
3, 4, 5, 6, 11, 12, 13, 14
7
8
9
10
15
16
Description
supply voltage
serial data input
parallel data output (open-drain)
master reset (active LOW)
output enable input (active LOW)
serial data output
storage register clock input
shift register clock input
ground (0 V)
NPIC6C596A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 October 2013
© NXP B.V. 2013. All rights reserved.
5 of 21
5 Page 
NXP Semiconductors
NPIC6C596A
Power logic 8-bit shift register; open-drain outputs
Qn
DUT
IF
t2
t1
t3
K(1)
0.85 mH
2500 μF
250 V
A(1)
0.1 A
15 V
IF
0
di/dt = 10 A/μs
25 % of lRM
RG
VI(2) G
driver
50 Ω
IRM
ta
trr
aaa-002560
(1) The open-drain Qn terminal under test is connected to testpoint K. All other terminals are connected together and connected to
testpoint A.
(2) The VI amplitude and RG are adjusted for dI/dt = 10 A/s. A VI double-pulse train is used to set IF = 0.1 A, where t1 = 10 s, t2 =
7 s and t3 = 3 s.
Fig 13. Test circuit and waveform for measuring reverse recovery current
NPIC6C596A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 October 2013
© NXP B.V. 2013. All rights reserved.
11 of 21
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| Páginas | Total 21 Páginas | |
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