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PDF 8V31012 Data sheet ( Hoja de datos )
| Número de pieza | 8V31012 | |
| Descripción | Differential HCSL Fanout Buffer | |
| Fabricantes | IDT | |
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1-to-12, Differential HCSL Fanout Buffer
8V31012
DATA SHEET
General Description
The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The
8V31012 is designed to translate any differential signal levels to
differential HCSL output levels. An external reference resistor is
used to set the value of the current supplied to an external
load/termination resistor. The load resistor value is chosen to equal
the value of the characteristic line impedance of 50. The 8V31012
is characterized at an operating supply voltage of 3.3V.
The differential HCSL outputs, accurate crossover voltage and duty
cycle make the 8V31012 ideal for interfacing to PCI Express and
FBDIMM applications.
Features
• Twelve differential HCSL outputs
• Translates any differential input signal (LVPECL, LVHSTL, LVDS,
HCSL) to HCSL levels without external bias networks
• Maximum output frequency: 250MHz
• Output skew: 265ps (typical)
• VOH: 850mV (maximum)
• Full 3.3V supply voltage
• Available in lead-free (RoHS 6) package
• -40°C to 85°C ambient operating temperature
Block Diagram
CLK
nCLK
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
IREF
8V31012 REVISION 1 10/21/15
Pin Assignment
Q0
nQ0
Q0
nQ0
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
VDD
nQ9
Q1
nQ1
VDD 3
Q1 4
34 Q9
33 GND
nQ1 5
32 nQ8
Q2 GND 6
31 Q8
nQ2
Q2 7
8V31012
30 VDD
Q3 nQ2 8
29 nQ7
nQ3
VDD 9
28 Q7
Q4
nQ4
Q5
Q3
nQ3
VDD
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
nQ6
Q6
nQ5
48-pin, 7mm x 7mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.
1 page  
8V31012 DATA SHEET
AC Electrical Characteristics
Table 3. HCSL AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C1, 2, 3
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tPD
tsk(o)
tsk(pp)
Output Frequency
Propagation Delay4
Output Skew5, 6
Part-to-Part Skew6, 7
Measured on at VOX
Measured on at VOX
250 MHz
2.35 2.75 ns
265 395 ps
335 ps
tjit
VMAX
VMIN
VCROSS
VCROSS
odc
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Absolute Max Output Voltage8
Absolute Min Output Voltage8
Absolute Crossing Voltage9, 10, 11
Total Variation of VCROSS over all
edges9, 10, 12
Rise/Fall Edge Rate13, 14
Rise/Fall Time Matching15
Output Duty Cycle16
CLK = 200MHz, Integration
Range: 12kHz – 30MHz
ƒ 150MHz
ƒ 150MHz
500
-150
250
0.15
0.6
45
ps
850 mV
150 mV
550 mV
140 mV
4.0 V/ns
20 %
55 %
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. Current adjust set for VOH = 0.7V. Measurements refer to PCIEX outputs only.
NOTE 3. Characterized using an RREF value of 950 resistor.
NOTE 4. Measured from the differential input cross point to the differential output crossing point.
NOTE 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross point.
NOTE 6. This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 8. Measurement using RREF = 950, RLOAD = 50.
NOTE 9. Measurement taken from single-ended waveform.
NOTE 10. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 11. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12. Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13. Measurement taken from differential waveform.
NOTE 14. Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 15. Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a ±75mV window centered on the
median cross point where Qx rising meets nQx falling.
NOTE 16. Assuming 50% input duty cycle. Data taken at ƒ 200MHz, unless otherwise specified.
REVISION 1 10/21/15
5 1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER
5 Page 
8V31012 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8V31012.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 8V31012 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VDD_MAX * (IDD_MAX) = 3.465V *(105mA) = 363.825mW
• Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 12 * 44.5mW = 534mW
Total Power_MAX = (3.465V, with all outputs switching) = 363.825mW + 534mW = 897.825mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 29°C/W per Table 4 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.898W *29°C/W = 111°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 4. Thermal Resistance JA for 48Lead VFQFN, E-Pad, Forced Convection
JA vs. Air Flow
Meters per Second
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
29.0°C/W
25.4°C/W
2.5
22.7°C/W
REVISION 1 10/21/15
11 1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER
11 Page | ||
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| PDF Descargar | [ Datasheet 8V31012.PDF ] | |
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