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Спецификация 74ALVCH16374 изготовлена «ON Semiconductor» и имеет функцию, называемую «Low-Voltage 16-Bit D-Type Flip-Flop». |
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Детали детали
Номер произв | 74ALVCH16374 |
Описание | Low-Voltage 16-Bit D-Type Flip-Flop |
Производители | ON Semiconductor |
логотип |
10 Pages
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74ALVCH16374
Low−Voltage 16−Bit D−Type
Flip−Flop with Bus Hold
1.8/2.5/3.3 V
(3−State, Non−Inverting)
The 74ALVCH16374 is an advanced performance, non−inverting
16−bit D−type flip−flop. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16374 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Clock Pulse inputs. These control pins can be tied together for full
16−bit operation.
The 74ALVCH16374 consists of 16 edge−triggered flip−flops with
individual D−type inputs and 3.6 V−tolerant 3−state outputs. The
clocks (CPn) and Output Enables (OEn) are common to all flip−flops
within the respective byte. The flip−flops will store the state of
individual D inputs that meet the setup and hold time requirements on
the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the
contents of the flip−flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. The OE input level
does not affect the operation of the flip−flops. The data inputs include
active bushold circuitry, eliminating the need for external pull−up
resistors to hold unused or floating inputs at a valid logic state.
• Designed for Low Voltage Operation: VCC = 1.65 − 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
7.8 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16374
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MARKING DIAGRAM
48
48
1
TSSOP−48
DT SUFFIX
CASE 1201
74ALVCH16374DT
AWLYYWW
1
A = Assembly
Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
CPn
D0−D15
O0−O15
Output Enable Inputs
Clock Pulse Inputs
Inputs
Outputs
ORDERING INFORMATION
Device
Package
74ALVCH16374DTR
TSSOP
Shipping
2500 / Reel
†To ensure the outputs activate in the 3−state condition, the output enable pins
should be connected to VCC through a pull−up resistor. The value of the resistor is
determined by the current sinking capability of the output connected to the OE pin.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 3
1
Publication Order Number:
74ALVCH16374/D
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74ALVCH16374
OE1 1
O0 2
O1 3
GND 4
O2 5
O3 6
VCC 7
O4 8
O5 9
GND 10
O6 11
O7 12
O8 13
O9 14
GND 15
O10 16
O11 17
VCC 18
O12 19
O13 20
GND 21
O14 22
O15 23
OE2 24
48 CP1
47 D0
46 D1
45 GND
44 D2
43 D3
42 VCC
41 D4
40 D5
39 GND
38 D6
37 D7
36 D8
35 D9
34 GND
33 D10
32 D11
31 VCC
30 D12
29 D13
28 GND
27 D14
26 D15
25 CP2
Figure 1. 48−Lead Pinout
(Top View)
1
OE1
48
CP1
47
D0
nCP
Q
D
2
O0
24
OE2
25
CP2
36
D8
nCP
Q
D
46
D1
nCP
Q
D
3
O1
35
D9
nCP
Q
D
44
D2
nCP
Q
D
5
O2
33
D10
nCP
Q
D
43
D3
nCP
Q
D
6
O3
32
D11
nCP
Q
D
41
D4
nCP
Q
D
8
O4
30
D12
nCP
Q
D
40
D5
nCP
Q
D
9
O5
29
D13
nCP
Q
D
38
D6
nCP
Q
D
11
O6
27
D14
nCP
Q
D
37
D7
nCP
Q
D
12
O7
26
D15
nCP
Q
D
Figure 2. Logic Diagram
1
OE1
CP1
48
25
CP2 24
OE2
EN1
EN2
EN3
EN4
D0 47
D1 46
D2 44
D3
D4
43
41
D5 40
D6 38
D7
D8
37
36
D9 35
D10 33
D11
D12
32
30
D13 29
D14 27
D15 26
1 1∇
1 2∇
1 3∇
1 4∇
2 O0
3 O1
5 O2
6
8
O3
O4
9 O5
11 O6
12
13
O7
O8
14 O9
16 O10
17
19
O11
O12
20 O13
22 O14
23 O15
Figure 3. IEC Logic Diagram
13
O8
14
O9
16
O10
17
O11
19
O12
20
O13
22
O14
23
O15
Inputs
Outputs
Inputs
Outputs
CP1 OE1 D0:7
O0:7
CP2
OE2
D8:15
O8:15
↑ LH H ↑LH H
↑ L L L ↑L L L
X L X O0 X L X O0
X H X Z XH X Z
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; ↑ = Low−to−High Transition; X = High or Low Voltage Level and
Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs. O0 = No Change.
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74ALVCH16374
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
TL
TJ
qJA
MSL
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
VI < GND
VO < GND
*0.5 to )4.6
*0.5 to )4.6
*0.5 to )4.6
*50
*50
$50
$100
$100
*65 to )150
260
)150
90
Level 1
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
FR
VESD
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30 to 35
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
UL 94 V−O @ 0.125 in
u2000
u200
N/A
V
ILATCH−UP Latch−Up Performance
Above VCC and Below GND at 125°C (Note 6)
$250
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max
VCC Supply Voltage
Operating
Data Retention Only
2.3
1.5
3.6
3.6
VI Input Voltage
VO Output Voltage
(Note 7)
(Active State)
(3−State)
−0.5
0
0
3.6
3.6
3.6
TA Operating Free−Air Temperature
*40
)85
Dt/DV
Input Transition Rise or Fall Rate
VCC = 2.5 V $ 0.2 V
VCC = 3.0 V $ 0.3 V
0
0
20
10
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
Unit
V
V
V
°C
ns/V
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