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Datasheet 74LVC125A Equivalent ( PDF ) |
N.º | Número de pieza | Descripción | Fabricantes | Category |
1 | 74LVC125A | LOW VOLTAGE CMOS QUAD BUS BUFFERS 74LVC125A
LOW VOLTAGE CMOS QUAD BUS BUFFERS (3-STATE) HIGH PERFORMANCE
s 5V TOLERANT INPUTS s HIGH SPEED: tPD = 4.8ns (MAX.) at VCC = 3V s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V s PCI BUS LEVELS GUARANTEED AT 24 mA s BALANCED | STMicroelectronics | buffer |
2 | 74LVC125A | Quad buffer/line driver 74LVC125A
Quad buffer/line driver with 5 V tolerant input/outputs; 3-state
Rev. 7 — 11 April 2013 Product data sheet
1. General description
The 74LVC125A consists of four non-inverting buffers/line drivers with 3-state outputs (nY) that are controlled by the output enable input (nOE). A HIGH at n | NXP Semiconductors | driver |
3 | 74LVC125A | QUADRUPLE 3-STATE BUFFERS 74LVC125A
QUADRUPLE 3-STATE BUFFERS
Description
The 74LVC125A provides four independent buffers with three state outputs. Each output is independently controlled by an associated output enable pin (OE) which places the device in the high impedance state when driven high. The device is designed for | Diodes | buffer |
4 | 74LVC125A | Low-Voltage CMOS Quad Buffer 74LVC125A
Low-Voltage CMOS Quad Buffer
With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting)
The 74LVC125A is a high performance, non−inverting quad buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input driver | ON Semiconductor | buffer |
74L Datasheet ( Hoja de datos ) - resultados coincidentes |
N.º | Número de pieza | Descripción | Fabricantes | Catagory |
1 | 74L74 | Dual Positive Edge Triggered D Flip-Flop National Semiconductor flip-flop | | |
2 | 74LCX00 | Low Voltage Quad 2-Input NAND Gate 74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
December 2013
74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Features
■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high i Fairchild Semiconductor gate | | |
3 | 74LCX00 | Low voltage CMOS QUAD 2-Input NAND gate 74LCX00
Low-voltage CMOS quad dual input NAND gate with 5 V tolerant inputs
Datasheet −production data
Features
■ 5 V tolerant inputs ■ High speed
– tPD = 4.3 ns (max.) at VCC = 3 V ■ Power-down protection on inputs and outputs ■ Symmetrical output impedance
– |IOH| = IOL = 24 mA (m ST Microelectronics gate | | |
4 | 74LCX00M | Low Voltage Quad 2-Input NAND Gate 74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
December 2013
74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Features
■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high i Fairchild Semiconductor gate | | |
5 | 74LCX00MTC | Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
March 1995 Revised March 1999
74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
General Description
The LCX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys Fairchild Semiconductor gate | | |
6 | 74LCX00MTCX | Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs 74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
March 1995 Revised March 1999
74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
General Description
The LCX00 contains four 2-input NAND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V sys Fairchild Semiconductor gate | | |
7 | 74LCX00SJ | Low Voltage Quad 2-Input NAND Gate 74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
December 2013
74LCX00 Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
Features
■ 5V tolerant inputs ■ 2.3V–3.6V VCC specifications provided ■ 5.2ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high i Fairchild Semiconductor gate | |
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