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PDF 74LVC574A Data sheet ( Hoja de datos )

Número de pieza 74LVC574A
Descripción Low-Voltage CMOS Octal D-Type Flip-Flop
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74LVC574A
Low-Voltage CMOS Octal
D-Type Flip-Flop
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74LVC574A is a high performance, non−inverting octal D−type
flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5 V allows 74LVC574A inputs to
be safely driven from 5 V devices.
The 74LVC574A consists of 8 edge−triggered flip−flops with
individual D−type inputs and 3−state true outputs. The buffered clock
and buffered Output Enable (OE) are common to all flip−flops. The
eight flip−flops will store the state of individual D inputs that meet the
setup and hold time requirements on the LOW−to−HIGH Clock (CP)
transition. With the OE LOW, the contents of the eight flip−flops are
available at the outputs. When the OE is HIGH, the outputs go to the
high impedance state. The OE input level does not affect the operation
of the flip−flops.
Features
Designed for 1.2 to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
ESD Performance:
Human Body Model >2000 V
Machine Model >200 V
These are Pb−Free Devices
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20
1
MARKING
DIAGRAM
20
TSSOP−20
DT SUFFIX
CASE 948E
1
LCV
574A
ALYWG
G
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 1
1
Publication Order Number:
74LVC574A/D

1 page




74LVC574A pdf
74LVC574A
AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns)
−40 to +855C
−40 to +1255C
Symbol
Parameter
Conditions
Typ
Min (Note 4) Max
Typ
Min (Note 4) Max
Unit
tpd Propagation Delay (Note 5)
CP to On
ten Enable Time (Note 6)
OE to On
tdis Disable Time (Note 7)
OE to On
tw Pulse Width
Clock HIGH or LOW
tsu Set−up Time
Dn to CP
th Hold Time
Dn to CP
fmax Maximum Frequency
VCC = 1.2 V
− 17.0 −
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
4.6
2.6
1.5
1.5
6.4 13.1 4.6
3.9 7.9 2.6
3.7 8.0 1.5
3.5 7.0 1.5
VCC = 1.2 V
− 19.0 −
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
1.5
1.5
1.5
1.5
7.0 17.1 1.5
4.0 9.4 1.5
4.1 8.5 1.5
3.2 7.5
1.5
VCC = 1.2 V
− 9.0 − −
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
2.5
1.0
1.5
1.5
4.1 10.1 2.5
2.3 5.7 1.0
3.1 6.5 1.5
2.9 6.0 1.5
VCC = 1.65 V to 1.95 V 5.0
− 5.0
VCC = 2.3 V to 2.7 V 4.0
− 4.0
VCC = 2.7 V
3.3 −
− 3.3
VCC = 3.0 V to 3.6 V 3.3 1.7 − 3.3
VCC = 1.65 V to 1.95 V 4.0
− 4.0
VCC = 2.3 V to 2.7 V 2.5
− 2.5
VCC = 2.7 V
2.0 −
− 2.0
VCC = 3.0 V to 3.6 V 2.0 0.3 − 2.0
VCC = 1.65 V to 1.95 V 3.0
− 3.0
VCC = 2.3 V to 2.7 V 2.0
− 2.0
VCC = 2.7 V
1.5 −
− 1.5
VCC = 3.0 V to 3.6 V 1.5 −0.2 − 1.5
VCC = 1.65 V to 1.95 V 100
− 80
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
125
150
− 100
− 120
VCC = 3.0 V to 3.6 V 150 200 − 120
15.1
9.1 ns
10.0
9.0
19.8
10.9 ns
11.0
9.5
11.6
6.6 ns
8.5
7.5
ns
ns
ns
MHz
tsk(0) Output Skew Time (Note 8)
− − 1.0 − − 1.5 ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
5. tpd is the same as tPLH and tPHL.
6. ten is the same as tPZL and tPZH.
7. tdis is the same as tPLZ and tPHZ.
8. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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