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Número de pieza | HMC1031 | |
Descripción | 0.1MHz to 500MHz Clock Generator | |
Fabricantes | Analog Devices | |
Logotipo | ||
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No Preview Available ! Data Sheet
0.1 MHz to 500 MHz Clock Generator
with Integer N PLL
HMC1031
FEATURES
Low current consumption: 1.95 mA typical
High phase frequency detector rate: 140 MHz
Hardware pin-programmable clock multiplication ratios:
1×/5×/10×
Lock detect indicator
Power-down mode (0.8 μA typical)
8-lead MSOP package: 4.9 mm × 3.0 mm
APPLICATIONS
Low jitter clock generation
Low bandwidth (BW) jitter attenuation
Low frequency phase-locked loops (PLLs)
Frequency translation
Oven controlled crystal oscillator (OCXO) frequency
multipliers
Phase lock clean high frequency references to 10 MHz
equipment
GENERAL DESCRIPTION
Together with an external loop filter and a voltage controlled
crystal oscillator (VCXO), the HMC1031 forms a complete
clock generator solution targeted at low frequency jitter
attenuation and reference clock generation applications.
The HMC1031 features a low power integer N divider, support-
ing divide ratios of 1, 5, and 10, which is controlled via external
hardware pins and requires no serial port.
FUNCTIONAL BLOCK DIAGRAM
VCC 1
REFIN 2
HMC1031
PFD/CP
8 GND
7 CP
LKDOP 3
D0 4
LKD 1/N
Figure 1.
6 VCOIN
5 D1
The integrated phase detector and charge pump are capable of
operating at up to 140 MHz, and a maximum VCXO input of
500 MHz ensures frequency compliance with a wide variety of
system clocks and VCXOs.
Additional features include an integrated lock detect indicator
available on a dedicated hardware pin, and a built in power-
down mode.
The HMC1031 is housed in an 8-lead MSOP package.
Rev. C
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Technical Support
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1 page Data Sheet
HMC1031
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC 1
8 GND
REFIN 2
LKDOP 3
HMC1031
TOP VIEW
(Not to Scale)
7 CP
6 VCOIN
D0 4
5 D1
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Description
1 VCC Supply Voltage (3.3 V Typical).
2
REFIN
Reference Input. REFIN is an externally ac-coupled reference frequency input.
3
LKDOP
Lock Detect Output, CMOS Drive.
4, 5
D0, D1
Integer N Division Ratio Selection. D0 and D1 are the CMOS inputs used to specify the integer N division ratio.
See Table 4.
6
VCOIN
Voltage Controlled Oscillator Input. VCOIN is an ac-coupled VCO/VCXO input.
7 CP Charge Pump Output.
8 GND Ground.
Table 4. Frequency Multiplication Truth Table
D0 D1 PLL Feedback Division Ratio (N)1
0 0 Power-down mode
1 0 Divide by 1
0 1 Divide by 5
1 1 Divide by 10
1 Set by SW1 in the evaluation PCB schematic (see Figure 24).
Rev. C | Page 5 of 13
5 Page Data Sheet
For example, to guarantee correct lock detector operation with
a 10 MHz reference (tPD = 100 ns) and no leakage into the VCO
VTUNE pin, the total capacitor leakage must be less than 1.5 µA.
A typical MLCC 33 nF, 25 V loop filter capacitor has approxi-
mately 0.5 nA of leakage (Murata GRM155R71E333KA88).
HMC1031
PRINTED CIRCUIT BOARD (PCB)
Use a sufficient number of via holes to connect the top and
bottom ground planes (see Figure 23). The evaluation circuit
board design is available from Analog Devices upon request.
U1
J3
R1
C1 Y4
R2
GND
Y1 R3
D0
R4
D1 LD
R31 D1 LDO
C5 C2
EXT REF
C4
SW1 TP1
J4
D0 TP2
R7 R10 R11
J3 C3 R6
TP3 TP4
C10
C12
J5 J6 C13
U1
C7
R12
C11
C14
R16
R8 R9
C8
C6
C9
C27
VTUNE
R5
Y2 TP5
XTAL
+3V
J7 R17
VCO
Y3
GND
C16
C15
TP6 C26
C18
U2
C20
C22
C19
R22
C21
C25
R30
C23
C24
R23
R19
R20 J8
C17
R24 EXT VCO
R25
TP7
GND
TP8
J4
J8
+5.5V
Figure 23. Evaluation PCB
J3
Rev. C | Page 11 of 13
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet HMC1031.PDF ] |
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