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PDF 6EDL04N06PT Data sheet ( Hoja de datos )
| Número de pieza | 6EDL04N06PT | |
| Descripción | High voltage gate driver IC | |
| Fabricantes | Infineon | |
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EiceDRIVER™
High voltage gate driver IC
6ED family - 2nd generation
3 phase 200 V and 600 V gate drive IC
6EDL04I06PT
6EDL04I06NT
6EDL04N06PT
6EDL04N02PR
EiceDRIVER™
datasheet
<Revision 2.6>, 05.08.2016
Industrial Power Control
1 page  
EiceDRIVER™
6ED family - 2nd generation
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Typical Application ...............................................................................................................................8
Block diagram for 6EDL04I06NT .........................................................................................................9
Block Diagram for 6EDL04I06PT, and 6EDL04N06PT / 6EDL04N02PR..........................................10
Pin Configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1)....................11
Input pin structure for negative logic (left) and positive logic (right)...................................................12
Input filter timing diagram for negative logic (left) and positive logic (right) .......................................12
EN pin structures................................................................................................................................12
/FAULT pin structures ........................................................................................................................13
Timing of short pulse suppression (6EDL04I06NT) ...........................................................................20
Timing of short pulse suppression (6EDL04I06PT, 6EDL04N06PT, 6EDL04N02PR) ......................20
Timing of of internal deadtime (input logic according to Table 1) ......................................................20
Enable delay time definition ...............................................................................................................21
Input to output propagation delay times and switching times definition (6EDL04I06NT) ..................21
Input to output propagation delay times and switching times definition (6EDL04I06PT,
6EDL04N06PT, 6EDL04N02PR) .......................................................................................................21
Operating areas (6EDL04I06NT, 6EDL04I06PT) ..............................................................................21
Operating Areas (6EDL04N06PT, 6EDL04N02PR)...........................................................................22
ITRIP-Timing ......................................................................................................................................22
Package drawing................................................................................................................................23
PCB reference layout .........................................................................................................................23
Package drawing................................................................................................................................24
PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint24
datasheet
5 <Revision 2.6>, 05.08.2016
5 Page 
EiceDRIVER™
6ED family - 2nd generation
3 Pin configuration, description, and functionality
1 VCC
2 HIN1
3 HIN2
4 HIN3
5 LIN1
6 LIN2
7 LIN3
8 FAULT
9 ITRIP
10 EN
11 RCIN
12 VSS
13 COM
14 LO3
VB1 28
HO1 27
VS1 26
nc 25
VB2 24
HO2 23
VS2 22
nc 21
VB3 20
HO3 19
VS3 18
nc 17
LO1 16
LO2 15
Figure 4 Pin Configuration of 6ED family (signals HIN1,2,3 and LIN1,2,3 according to Table 1)
Table 2
Symbol
VCC
VSS
HIN1,2,3
LIN1,2,3
/FAULT
EN
ITRIP
RCIN
COM
VB1,2,3
HO1,2,3
VS1,2,3
LO1,2,3
nc
xPin Description
Description
Low side power supply
Logic ground
High side logic input (positive or negative logic according to Table 1)
Low side logic input (positive or negative logic according to Table 1)
Indicates over-current and under-voltage (negative logic, open-drain output)
Enable I/O functionality (positive logic)
Analog input for over-current shut down, activates FAULT and RCIN to VSS
External RC-network to define FAULT clear delay after FAULT-Signal (TFLTCLR)
Low side gate driver reference
High side positive power supply
High side gate driver output
High side negative power supply
Low side gate driver output
Not connected
3.1 Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7)
The Schmitt trigger input threshold of them are such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. Input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses
according to Figure 5 and Figure 6.
datasheet
11 <Revision 2.6>, 05.08.2016
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet 6EDL04N06PT.PDF ] | |
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