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PDF W989D2KB Data sheet ( Hoja de datos )

Número de pieza W989D2KB
Descripción 512Mb Mobile LPSDR
Fabricantes Winbond 
Logotipo Winbond Logotipo



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No Preview Available ! W989D2KB Hoja de datos, Descripción, Manual

W989D6KB / W989D2KB
1. GENERAL DESCRIPTION
512Mb Mobile LPSDR
The Winbond 512Mb Low Power SDRAM is a low power synchronous memory containing
536,870,912 memory cells fabricated with Winbond high performance process technology.
It is designed to consume less power than the ordinary SDRAM with low power features essential
for applications which use batteries. It is available in two organizations: 4,194,304-words × 4 banks
× 32 bits or 8,388,608 words × 4 banks × 16 bits. The device operates in a fully synchronous
mode, and the output data are synchronized to positive edges of the system clock and is capable
of delivering data at clock rate up to 166MHz. The device supports special low power functions
such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh
(ATCSR).
The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile
game consoles and other handheld applications where large memory density and low power
consumption are required. The device operates from 1.8V power supply, and supports the 1.8V
LVCMOS bus interface.
2. FEATURES
Power supply VDD = 1.7V~1.95V
VDDQ = 1.7V~1.95V
Frequency : 166MHz(-6)
Standard Self Refresh Mode
Programmable Partial Array Self Refresh
Power Down Mode
Deep Power Down Mode (DPD)
Programmable output buffer driver strength
Automatic Temperature Compensated Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Refresh: refresh cycle 64ms
Interface: LVCMOS
Support package :
54 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended (-25°C ~ +85°C)
Industrial (-40°C ~ +85°C)
-1-
Publication Release Date : October 07, 2013
Revision : A01-003

1 page




W989D2KB pdf
W989D6KB / W989D2KB
4. PIN CONFIGURATION
4.1 Ball Assignment: LPSDR X 16
1
A VSS
B DQ14
C DQ12
D DQ10
E DQ8
F UDQM
G A12
H A8
J VSS
2
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
4.2 Ball Assignment: LPSDR X 32
1
A DQ26
B DQ28
C VSSQ
D VSSQ
E VDDQ
F VSS
G A4
H A7
J CLK
K DQM1
L VDDQ
M VSSQ
N VSSQ
P DQ11
R DQ13
2
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
54Ball VFBGA
3 456
7
VSSQ
VDDQ
VDDQ
VSSQ
VSSQ
VDDQ
VDDQ
VSSQ
VSS
VDD
CKE
CAS
A9 BA0
A6 A0
A4 A3
(Top View) Pin Configuration
90Ball VFBGA
3 456
7
VSS
VSSQ
DQ25
DQ30
NC
A3
VDD
VDDQ
DQ22
DQ17
NC
A2
A6
A12
A9
NC
VSS
DQ9
DQ14
A10
NC
BA0
CAS
VDD
DQ6
DQ1
VSSQ
VSS
VDDQ
VDD
(Top View) Pin Configuration
512Mb Mobile LPSDR
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
A2
9
VDD
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
VDD
8
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BA1
CS
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
9
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ2
-5-
Publication Release Date : October 07, 2013
Revision : A01-003

5 Page





W989D2KB arduino
W989D6KB / W989D2KB
(x32)
Parameter
Operating current:
Active mode; burst = 1; READ or WRITE; tRC = tRC (MIN)
Standby current:
Power-down mode; All banks idle; CKE = LOW
Standby current:
Nonpower-down mode; All banks idle; CKE = HIGH
Standby current:
Active mode; CKE = LOW; CS# = HIGH; All banks active;
No accesses in progress
Standby current:
Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD
met; No accesses in progress
Operating current:
Burst mode; READ or WRITE; All banks active; Half of DQ toggling
every cycle
Auto refresh current:; tRFC=tRFC (MIN)
CKE = HIGH; CS# = HIGH
Deep Power Down Mode
512Mb Mobile LPSDR
-6 -75
Sym.
Unit Notes
Max. Max.
IDD1 38 35 mA 2, 3, 4
Idd2P 0.3 0.3 mA
5
Idd2N 10 10 mA
Idd3P 3
3 mA 3, 4, 6
Idd3N 25 25 mA 3, 4, 6
Idd4 75 70 mA 2, 3, 4
Idd5 75
Izz 10
75 mA 2, 3, 4, 6
10 μA
5,8
- 11 -
Publication Release Date : October 07, 2013
Revision : A01-003

11 Page







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