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PDF W966K6HB Data sheet ( Hoja de datos )
| Número de pieza | W966K6HB | |
| Descripción | CellularRAM | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W966K6HB
32Mb Async./Page,Syn./Burst CellularRAM
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ........................................................................................................ 4
2. FEATURES................................................................................................................................ 4
3. ORDERING INFORMATION ..................................................................................................... 4
4. PIN CONFIGURATION.............................................................................................................. 5
4.1 Ball Assignment................................................................................................................................. 5
5. PIN DESCRIPTION.................................................................................................................... 6
5.1 Signal Description ............................................................................................................................. 6
6. BLOCK DIAGRAM .................................................................................................................... 7
6.1 Block Diagram ................................................................................................................................... 7
6.2 CellularRAM - Interface Configuration Options .................................................................................. 8
7. INSTRUCTION SET................................................................................................................... 9
7.1 Bus Operation ................................................................................................................................... 9
8. FUNCTIONAL DESCRIPTION ................................................................................................ 10
8.1 Power Up Initialization ..................................................................................................................... 10
8.1.1 Power-Up Initialization Timing...................................................................................................................... 10
8.2 Bus Operating Modes...................................................................................................................... 10
8.2.1 Asynchronous Modes ................................................................................................................................... 10
8.2.1.1 READ Operation(ADV# LOW) .................................................................................................................................11
8.2.1.2 WRITE Operation (ADV# LOW)...............................................................................................................................11
8.2.2 Page Mode READ Operation ....................................................................................................................... 12
8.2.2.1 Page Mode READ Operation (ADV# LOW) .............................................................................................................12
8.2.3 BURST Mode Operation .............................................................................................................................. 12
8.2.3.1 Burst Mode READ (4-word burst) ............................................................................................................................13
8.2.3.2 Burst Mode WRITE (4-word burst)...........................................................................................................................14
8.2.3.3 Refresh Collision During Variable-Latency READ Operation ...................................................................................15
8.2.4 Mixed-Mode Operation ................................................................................................................................. 16
8.2.4.1 WAIT Operation .......................................................................................................................................................16
8.2.4.2 Wired-OR WAIT Configuration.................................................................................................................................16
8.2.5 LB#/ UB# Operation ..................................................................................................................................... 17
8.3 Low Power Operation ...................................................................................................................... 17
8.3.1 Standby Mode Operation ............................................................................................................................. 17
8.3.2 Temperature Compensated Refresh............................................................................................................ 17
8.3.3 Partial Array Refresh .................................................................................................................................... 17
8.3.4 Deep Power-Down Operation ...................................................................................................................... 17
8.4 Registers ......................................................................................................................................... 18
8.4.1 Access Using CRE ....................................................................................................................................... 18
8.4.1.1 Configuration Register WRITE, Asynchronous Mode Followed by READ ARRAY Operation .................................18
8.4.1.2 Configuration Register WRITE – CE# control .......................................................................................................19
8.4.1.3 Configuration Register WRITE, Synchronous Mode Followed by READ ARRAY Operation ...................................20
8.4.1.4 Register READ, Asynchronous Mode Followed by READ ARRAY Operation .........................................................21
8.4.1.5 Register READ, Synchronous Mode Followed by READ ARRAY Operation...........................................................22
8.4.2 Software Access........................................................................................................................................... 23
8.4.2.1 Load Configuration Register ....................................................................................................................................23
8.4.2.2 Read Configuration Register....................................................................................................................................24
8.4.3 Bus Configuration Register .......................................................................................................................... 24
8.4.3.1 Bus Configuration Register Definition ......................................................................................................................25
8.4.3.2 Burst Length (BCR[2:0]) Default = Continuous Burst ...............................................................................................26
8.4.3.3 Burst Wrap (BCR[3]) Default = No Wrap..................................................................................................................26
8.4.3.4 Sequence and Burst Length.....................................................................................................................................27
8.4.3.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength.....................................................................28
8.4.3.6 Table of Drive Strength ............................................................................................................................................28
Publication Release Date: Nov. 07, 2014
Revision: A01-002
-1-
1 page  
4. PIN CONFIGURATION
4.1 Ball Assignment
123 4
A
LB# OE#
A0
A1
B
DQ8
UB#
A3
A4
C
DQ9
DQ10
A5
A6
D
VSSQ
DQ11
A17
A7
E
VCCQ
DQ12
NC
A16
F
DQ14
DQ13
A14
A15
G
DQ15
A19
A12
A13
H A18 A8 A9 A10
J
WAIT CLK ADV#
NC
(Top View) Pin Configuration
W966K6HB
5
A2
CE#
DQ1
DQ3
DQ4
DQ5
WE#
A11
NC
6
CRE
DQ0
DQ2
VCC
VSS
DQ6
DQ7
A20
NC
Publication Release Date: Nov. 07, 2014
Revision: A01-002
-5-
5 Page 
W966K6HB
8.2.1.1 READ Operation(ADV# LOW)
CE #
OE #
WE #
ADDRESS
DATA
Address Valid
Data Valid
LB # / UB #
Note:
ADV must remain LOW for PAGE MODE operation.
tRC = READ Cycle Time
8.2.1.2 WRITE Operation (ADV# LOW)
CE #
Don ‘ t Care
OE #
WE #
<tCEM
ADDRESS
DATA
Address Valid
Data Valid
LB # / UB #
tWC = WRITE Cycle Time
Don’t Care
- 11 -
Publication Release Date: Nov. 07, 2014
Revision: A01-002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W966K6HB.PDF ] | |
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