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PDF W958D6DB Data sheet ( Hoja de datos )
| Número de pieza | W958D6DB | |
| Descripción | A/D MUX | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W958D6DB
256Mb Async./Burst/Sync./A/D MUX
1. GENERAL DESCRIPTION
Winbond x16 ADMUX products are high-speed, CMOS pseudo-static random access memory developed for low-
power, portable applications. The device has a DRAM core organized. These devices are a variation of the industry-
standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality
dramatically reduce the required signal count, and increase READ/WRITE bandwidth.
For seamless operation on a burst Flash bus, Winbond x16 ADMUX products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and has no
significant impact on device READ/WRITE performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the
Winbond x16 ADMUX device interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up and can be updated
anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. Winbond x16 ADMUX
products include two mechanisms to minimize standby current. Partial-array refresh (PAR) enables the system to limit
refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR)
uses an on-chip sensor to adjust the refresh rate to match the device temperature—the refresh rate decreases at
lower temperatures to minimize current consumption during standby. The system-configurable refresh mechanisms
are accessed through the RCR.
Winbond x16 ADMUX is compliant with the industry-standard CellularRAM 1.5 x16 A/D MUX.
2. FEATURES
•Supports asynchronous and burst operations
• VCC, VCCQ Voltages:
1.7V–1.95V VCC
1.7V–1.95V VCCQ
• Random access time: 70ns
• Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 133 MHz (tCLK = 7.5ns)
• Low power consumption:
Asynchronous READ: <25 mA
Continuous burst READ: <35 mA
Standby current: 400μA
• Low-power features
On-chip temperature compensated refresh (TCR)
Partial array refresh (PAR)
Deep power-down (DPD) mode
Package: 54 Ball VFBGA
16-bit multiplexed address/data bus
Operating temperature range : -40°C~85°C
Publication Release Date : June 27 ,2013
- 1 - Revision : A01-003
1 page  
W958D6DB
256Mb Async./Burst/Sync./A/D MUX
4. PIN CONFIGURATION
4.1 Ball Assignment
1 2 3 45 6
A LB# OE# NC NC NC CRE
B
ADQ8
UB#
NC
NC CE# ADQ0
C
ADQ9 ADQ10
NC
NC ADQ1 ADQ2
D
VSSQ ADQ11
A17
NC ADQ3 VCC
E
VCCQ ADQ12
A21
A16 ADQ4 VSS
F
ADQ14 ADQ13
NC
NC ADQ5 ADQ6
G
ADQ15
A19
NC
NC
WE#
ADQ7
H A18 NC NC NC NC A20
J
WAIT
CLK
ADV#
A22
A23
NC
(Top View) Pin Configuration
Publication Release Date : June 27 ,2013
- 5 - Revision : A01-003
5 Page 
W958D6DB
256Mb Async./Burst/Sync./A/D MUX
8.2.2 Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a
multi-clock sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is
latched on the first CLK edge after ADV# LOW. During this first clock rising edge, WE# indicates whether the
operation is going to be a READ (WE# = HIGH) or WRITE (WE# =LOW).
8.2.2.1 Burst Mode READ (4-word burst)
CLK
A[max:16]
Valid
address
ADV#
CE#
Latency Code 2(3 clocks)
OE#
WE#
LB#/UB#
A/DQ[15:0]
Valid
address
D0 D1 D2 D3
WAIT
READ burst identified
(WE#=HIGH)
Invalid
Don’t Care
Undefined
Note : Non-default BCR settings for burst mode READ (4-word burst): fixed or variable latency, Latency code 2 (3 clocks), WAIT
active Low, WAIT asserted during delay. Diagram is representative of variable latency with no refresh collision or fixed-
latency access.
- 11 -
Publication Release Date : June 27 ,2013
Revision : A01-003
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W958D6DB.PDF ] | |
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