|
|
PDF 74HCT4060-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74HCT4060-Q100 | |
| Descripción | 14-stage binary ripple counter | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74HCT4060-Q100 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
|
No Preview Available !
74HC4060-Q100;
74HCT4060-Q100
14-stage binary ripple counter with oscillator
Rev. 2 — 10 April 2013
Product data sheet
1. General description
The 74HC4060-Q100; 74HCT4060-Q100 are high-speed Si-gate CMOS devices that
comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky
TTL (LSTTL).
The 74HC4060-Q100; 74HCT4060-Q100 are 14-stage ripple-carry counter/dividers and
oscillators with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (Q3 to
Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator
configuration allows design of either RC or crystal oscillator circuits. The oscillator may be
replaced by an external clock signal at input RS. In this case keep the other oscillator pins
(RTC and CTC) floating. The counter advances on the negative-going transition of RS. A
HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of
other input conditions. In the HCT version, the MR input is TTL compatible, but the RS
input has CMOS input switching levels and can be driven by a TTL output by using a
pull-up resistor to VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
All active components on chip
RC or crystal oscillator configuration
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Control counters
Timers
Frequency dividers
Time-delay circuits
1 page  
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
7. Functional description
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384
RS
MR
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q11
Q12
Q13
Fig 7. Timing diagram
001aai117
8. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
IOK output clamping current
IO output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
+7
20
20
25
V
mA
mA
mA
ICC
IGND
Tstg
supply current
ground current
storage temperature
- 50 mA
50 -
mA
65 +150 C
74HC_HCT4060_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 April 2013
© NXP B.V. 2013. All rights reserved.
5 of 25
5 Page 
NXP Semiconductors
74HC4060-Q100; 74HCT4060-Q100
14-stage binary ripple counter with oscillator
Table 6. Dynamic characteristics …continued
GND = 0 V; CL = 50 pF unless otherwise specified; for test circuit see Figure 11.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
fmax maximum RS; see Figure 8
frequency
VCC = 2.0 V
6 26 -
4.8
-
4
- MHz
VCC = 4.5 V
30 80 -
24
-
20
- MHz
VCC = 5.0 V; CL = 15 pF
- 87 -
-
-
-
- MHz
VCC = 6.0 V
35 95 -
28
-
24
- MHz
CPD power
VI = GND to VCC;
[4] - 40 -
-
-
-
- pF
dissipation VCC = 5 V; fi = 1 MHz
capacitance
74HCT4060-Q100
tpd
propagation RS to Q3; see Figure 8
[1]
delay
VCC = 4.5 V
- 33 66
-
83
-
99 ns
VCC = 5.0 V; CL = 15 pF
- 31 -
-
-
-
- ns
Qn to Qn+1; see Figure 9 [2]
VCC = 4.5 V
- 8 16
-
20
-
24 ns
VCC = 5.0 V; CL = 15 pF
-6-
-
-
-
- ns
tPHL HIGH to LOW MR to Qn; see Figure 10
propagation
delay
VCC = 4.5 V
- 21 44
-
55
-
66 ns
VCC = 5.0 V; CL = 15 pF
- 18 -
-
-
-
- ns
tt transition time Qn; see Figure 8
[3]
VCC = 4.5 V
- 7 15
-
19
-
22 ns
tW pulse width RS (HIGH or LOW);
see Figure 8
VCC = 4.5 V
16 6 -
20
-
24
- ns
MR (HIGH); see Figure 10
VCC = 4.5 V
16 6 -
20
-
24
- ns
trec recovery time MR to RS; see Figure 10
VCC = 4.5 V
26 13 -
33
-
39
- ns
fmax maximum RS; see Figure 8
frequency
VCC = 4.5 V
30 80 -
24
-
20
- MHz
VCC = 5.0 V; CL = 15 pF
- 88 -
-
-
-
- MHz
74HC_HCT4060_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 April 2013
© NXP B.V. 2013. All rights reserved.
11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet 74HCT4060-Q100.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74HCT4060-Q100 | 14-stage binary ripple counter | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |