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8T49N285 PDF даташит

Спецификация 8T49N285 изготовлена ​​​​«Integrated Device Technology» и имеет функцию, называемую «NG Octal Universal Frequency Translator».

Детали детали

Номер произв 8T49N285
Описание NG Octal Universal Frequency Translator
Производители Integrated Device Technology
логотип Integrated Device Technology логотип 

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8T49N285 Даташит, Описание, Даташиты
FemtoClock® NG Octal Universal
Frequency Translator
8T49N285
Datasheet
General Description
The 8T49N285 has a fractional-feedback PLL that can be used as a
jitter attenuator or frequency translator. It is equipped with six integer
and two fractional output dividers, allowing the generation of up to 8
different output frequencies, ranging from 8kHz to 1GHz. Three of
these frequencies are completely independent of each other and the
inputs. The other five are related frequencies. The eight outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N285 accepts up to two differential or single-ended input
clocks and a crystal input. The PLL can lock to either input clock, but
both input clocks must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS). It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N285 supports holdover with an initial accuracy of ±50ppB
from the point where the loss of all applicable input reference(s) has
been detected. It maintains a historical average operating point that
may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
The PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• OTN de-mapping (Gapped Clock and DCO mode)
• Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
• SyncE (G.8262) applications
• Wireless base station baseband
• Data communications
• 100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS typical jitter (including spurs),12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover & Loss-of-Signal status outputs
Open-drain Interrupt pin
Nine programmable PLL loop bandwidth settings from 1.4Hz to
360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C or via external I2C EEPROM
Bypass clock paths for system tests
Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free RoHs (6)
©2016 Integrated Device Technology, Inc.
1
Revision 5, October 26, 2016









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8T49N285 Даташит, Описание, Даташиты
8T49N285 Datasheet
8T49N285 Block Diagram
XTAL
CLK0
CLK1
OSC Input Clock
Monitoring,
÷ P0
Priority,
&
÷ P1 Selection
Fractional
Feedback
APLL
Lock
Holdover
IntN Output
Divider
IntN Output
Divider
FracN Output
Divider
FracN Output
Divider
Q0
Q1
Q2
Q3
nRST
SCLK
SDATA
Reset
Logic
I2C Master
LOS
OTP
I2C Slave
Status Registers
Control Registers
GPIO
Logic
4
IntN
IntN
IntN
IntN
Serial EEPROM
SA0
GPIO
nINT PLL_BYP
Figure 1. 8T49N285 Functional Block Diagram
Q4
Q5
Q6
Q7
©2016 Integrated Device Technology, Inc.
2
Revision 5, October 26, 2016









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8T49N285 Даташит, Описание, Даташиты
Pin Assignment
nQ1
Q1
VCCO1
nRST
nQ0
Q0
VCCO0
nINT
VCCA
CAP_REF
CAP
PLL_BYP
VCCA
VCCA
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 28
44 27
45 26
46 25
47 24
48 23
49 22
50
8T49N285
21
51 20
52 19
53 18
54 17
55 16
56 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
nQ2
Q2
VCCO2
GPIO[0]
nQ3
Q3
VCCO3
GPIO[1]
VCCA
RESERVED
RESERVED
VCC
VCCA
VCCA
56-pin, 8mm x 8mm VFQFN Package
Figure 2. Pin-out Drawing
8T49N285 Datasheet
©2016 Integrated Device Technology, Inc.
3
Revision 5, October 26, 2016










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