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8T49N287 PDF даташит

Спецификация 8T49N287 изготовлена ​​​​«Integrated Device Technology» и имеет функцию, называемую «NG Octal Universal Frequency Translator».

Детали детали

Номер произв 8T49N287
Описание NG Octal Universal Frequency Translator
Производители Integrated Device Technology
логотип Integrated Device Technology логотип 

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8T49N287 Даташит, Описание, Даташиты
FemtoClock® NG Octal Universal
Frequency Translator
8T49N287
Datasheet
General Description
The 8T49N287 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to 8 different output frequencies, ranging from
8kHz to 1GHz. Four of these frequencies are completely
independent of each other and the inputs. The other four are related
frequencies. The eight outputs may select among LVPECL, LVDS,
HCSL or LVCMOS output levels.
This makes it ideal to be used in any frequency translation
application, including 1G, 10G, 40G and 100G Synchronous
Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC
rates. The device may also behave as a frequency synthesizer.
The 8T49N287 accepts up to two differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. Each
PLL can use the other input for redundant backup of the primary
clock, but in this case, both input clocks must be related in frequency.
The device supports hitless reference switching between input clocks.
The device monitors all input clocks for Loss of Signal (LOS), and
generates an alarm when an input clock failure is detected. Automatic
and manual hitless reference switching options are supported. LOS
behavior can be set to support gapped or un-gapped clocks.
The 8T49N287 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency conver-
sion, supporting all FEC rates, including the new revision of ITU-T
Recommendation G.709 (2009), most with 0ppm conversion error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also
supports I2C master capability to allow the register configuration to
be read from an external EEPROM.
Applications
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output
clocks
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover & Loss-of-Signal status outputs
Open-drain Interrupt pin
Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz.
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I2C or via external I2C EEPROM
Bypass clock paths for system tests
Power supply modes
VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free (RoHS 6)
©2016 Integrated Device Technology, Inc.
1
Revision 7, October 27, 2016









No Preview Available !

8T49N287 Даташит, Описание, Даташиты
8T49N287 Datasheet
8T49N287 Block Diagram
XTAL
CLK0
CLK1
OSC
÷ P0
÷ P1
Input Clock
Monitoring,
Priority,
&
Selection
Fractional
Feedback
APLL 0
Lock 0
Holdover 0
Fractional
Feedback
APLL 1
Lock 1
Holdover 1
nRST
SCLK
SDATA
Reset
Logic
I2C Master
LOS
OTP
I2C Slave
Status Registers
Control Registers
IntN Output
Divider
IntN Output
Divider
FracN Output
Divider
FracN Output
Divider
GPIO
Logic
4
IntN
IntN
IntN
IntN
Serial EEPROM
SA0
Figure 1. 8T49N287 Functional Block Diagram
GPIO
nINT PLL_BYP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
©2016 Integrated Device Technology, Inc.
2
Revision 7, October 27, 2016









No Preview Available !

8T49N287 Даташит, Описание, Даташиты
Pin Assignment
nQ1
Q1
VCCO1
nRST
nQ0
Q0
VCCO0
nINT
VCCA
CAP0_REF
CAP0
PLL_BYP
VCCA
VCCA
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43 28
44 27
45 26
46 25
47 24
48 23
49 22
50
8T49N287
21
51 20
52 19
53 18
54 17
55 16
56 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
nQ2
Q2
VCCO2
GPIO[0]
nQ3
Q3
VCCO3
GPIO[1]
VCCA
CAP1_REF
CAP1
VCC
VCCA
VCCA
56-pin, 8mm x 8mm VFQFN Package
Figure 2. Pinout Drawing
8T49N287 Datasheet
©2016 Integrated Device Technology, Inc.
3
Revision 7, October 27, 2016










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