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Número de pieza | NSBA114EF3 | |
Descripción | Digital Transistors | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de NSBA114EF3 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! MUN2111, MMUN2111L,
MUN5111, DTA114EE,
DTA114EM3, NSBA114EF3
Digital Transistors (BRT)
R1 = 10 kW, R2 = 10 kW
PNP Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a base−
emitter resistor. The BRT eliminates these individual components by
integrating them into a single device. The use of a BRT can reduce
both system cost and board space.
Features
• Simplifies Circuit Design
• Reduces Board Space
• Reduces Component Count
• S and NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC-Q101 Qualified
and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS (TA = 25°C)
Rating
Symbol
Max
Unit
Collector−Base Voltage
Collector−Emitter Voltage
VCBO
VCEO
50
50
Vdc
Vdc
Collector Current − Continuous
IC 100 mAdc
Input Forward Voltage
VIN(fwd)
40
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
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PIN CONNECTIONS
PIN 3
COLLECTOR
PIN 1
BASE
R1
(OUTPUT)
(INPUT) R2
PIN 2
EMITTER
(GROUND)
MARKING DIAGRAMS
XX MG
G
1
SC−59
CASE 318D
STYLE 1
XXX MG
G
1
SOT−23
CASE 318
STYLE 6
XX MG
G
1
XX M
1
SC−70/SOT−323
CASE 419
STYLE 3
SC−75
CASE 463
STYLE 1
XX M
1
XM 1
SOT−723
CASE 631AA
STYLE 1
SOT−1123
CASE 524AA
STYLE 1
XXX
M
G
= Specific Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking, and shipping information in
the package dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
December, 2013 − Rev. 7
1
Publication Order Number:
DTA114E/D
1 page MUN2111, MMUN2111L, MUN5111, DTA114EE, DTA114EM3, NSBA114EF3
1
IC/IB = 10
0.1
TYPICAL CHARACTERISTICS
MUN2111, MMUN2111L, MUN5111, DTA114EE, DTA114EM3
1000
TA = −25°C
75°C
25°C
100
VCE = 10 V
TA = 75°C
−25°C
25°C
0.01
0
10
9
8
7
6
5
4
3
2
1
0
0
20 40 60
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) vs. IC
10
80 1
10
IC, COLLECTOR CURRENT (mA)
Figure 3. DC Current Gain
100
f = 10 kHz
lE = 0 A
TA = 25°C
100 75°C 25°C
10 TA = −25°C
1
0.1
10 20 30 40
VR, REVERSE VOLTAGE (V)
Figure 4. Output Capacitance
0.01
VO = 5 V
0.001
50 0 1 2 3 4 5 6 7 8 9 10
Vin, INPUT VOLTAGE (V)
Figure 5. Output Current vs. Input Voltage
100
VO = 0.2 V
10 TA = −25°C
25°C
75°C
1
0.1
0
10
20 30
40
IC, COLLECTOR CURRENT (mA)
Figure 6. Input Voltage vs. Output Current
50
http://onsemi.com
5
5 Page MUN2111, MMUN2111L, MUN5111, DTA114EE, DTA114EM3, NSBA114EF3
PACKAGE DIMENSIONS
−X−
D
b1
3
−Y−
E
2X e
12
2X b
0.08 X Y
TOP VIEW
3X L
1
3X L2
BOTTOM VIEW
SOT−723
CASE 631AA
ISSUE D
A
HE
C
SIDE VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MILLIMETERS
DIM MIN NOM MAX
A 0.45 0.50 0.55
b 0.15 0.21 0.27
b1 0.25 0.31 0.37
C 0.07 0.12 0.17
D 1.15 1.20 1.25
E 0.75 0.80 0.85
e 0.40 BSC
H E 1.15 1.20 1.25
L 0.29 REF
L2 0.15 0.20 0.25
STYLE 1:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
RECOMMENDED
SOLDERING FOOTPRINT*
2X 0.27
2X
0.40
PACKAGE
OUTLINE
1.50
3X 0.52
0.36
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet NSBA114EF3.PDF ] |
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