PDF HD74HC175 Data sheet ( Hoja de datos )

Número de pieza	HD74HC175
Descripción	Quad. D-type Flip-Flops
Fabricantes	Renesas
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Hay una vista previa y un enlace de descarga de HD74HC175 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas
No Preview Available ! HD74HC175 Quad. D-type Flip-Flops (with Clear) REJ03D0585-0300 Rev.3.00 Jan 31, 2006 Description Information at the D inputs of the HD74HC175 is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and compliment outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and a common clear. Clearing is accomplished by a negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four Q outputs to a logic high level. Features • High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: VCC = 2 to 6 V • Low Input Current: 1 µA max • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC175P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74HC175TELL TSSOP-16 pin PTSP0016JB-A (TTP-16DAV) T Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) — ELL (2,000 pcs/reel) Function Table Clear L H H H H : High level L : Low level X : Irrelevant Inputs Clock X L D X H L X Output QQ LH HL LH no change Rev.3.00, Jan 31, 2006 page 1 of 6 1 page HD74HC175 Waveforms • Waveform – 1 tr tf Data Clock Q Q 10 % 90 % 50 % tsu tr 90 % 50 % th tf 10 % tsu 50 % th 10 % 90 % 50 % 50 % tw tPLH 10 % 90 % 50 % tTLH tPHL 10 % tw 50 % tPHL 90 % 50 % 10 % tTHL tPLH 50 % 10 % 50 % 10 % 90 % tTHL tTLH VCC 0V VCC 0V VOH VOL VOH VOL • Waveform – 2 tf tr Clear Clock Q Q 90 % 90 % 50 % 10 % 50 % 10 % tw tf tr tPHL 90 % 50 % 10 % trem tw 90 % 50 % 10 % tPLH 90 % 50 % 10 % 90 % 50 % 10 % tTHL tPLH 50 % 10 % 90 % tTLH tPHL 90 % 50 % 10 % tTLH Note : Clock Input : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns Data Input : PRR ≤ 500 kHz tTHL VCC 0V VCC 0V VOH VOL VOH VOL Rev.3.00, Jan 31, 2006 page 5 of 6 5 Page

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