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PDF HD74HC4020 Data sheet ( Hoja de datos )
| Número de pieza | HD74HC4020 | |
| Descripción | 14-stage Binary Counter | |
| Fabricantes | Renesas | |
| Logotipo |  |
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HD74HC4020
14-stage Binary Counter
REJ03D0645-0200
(Previous ADE-205-531)
Rev.2.00
Mar 30, 2006
Description
The HD74HC4020 is a 14 stage counter. This device is incremented on the falling edge (negative transition) of the
input clock, and all its output is reset to a low level by applying a logical high on its reset input.
Features
• High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC4020P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
HD74HC4020FPEL SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
Function Table
Clock
X
Note: 1. X: Don’t care
Reset
L
L
H
Outputs State
No change
Advance to next state
All output are low
Rev.2.00 Mar 30, 2006 page 1 of 6
1 page  
HD74HC4020
Waveforms
• Waveform – 1
Reset
Clock
Q1
tf
90%
10%
tf
tf
90%
50% 50%
tw
10%
tw
tPLH
10%
90%
50%
tTLH
90%
50% 50%
10%
tPHL
90%
50%
10%
tTHL
Note : 1. Waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
• Waveform – 2
Reset
tr tf
10%
90%
50%
90%
50%
10%
tw trem
Clock
tPHL
90%
50%
10%
Any Q
90%
50%
10%
tTHL
Note : 1. Waveform : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
VCC
0V
VCC
0V
VOH
VOL
VCC
0V
VCC
0V
VOH
VOL
Rev.2.00 Mar 30, 2006 page 5 of 6
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HD74HC4020.PDF ] | |
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