74HCU04 PDF даташит
Спецификация 74HCU04 изготовлена «ON Semiconductor» и имеет функцию, называемую «Hex Unbuffered Inverter». |
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Детали детали
Номер произв | 74HCU04 |
Описание | Hex Unbuffered Inverter |
Производители | ON Semiconductor |
логотип |
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74HCU04
Hex Unbuffered Inverter
High−Performance Silicon−Gate CMOS
The 74HCU04 is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of six single−stage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a high−input impedance amplifier. For digital
applications, the HC04 is recommended.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6.0 V in Oscillator
Configurations
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7.0 A Requirements
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 12 FETs or 3 Equivalent Gates
• These are Pb−Free Devices
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HCU04G
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HCU
04
ALYWG
1G
HCU04
A
L, WL
Y
W, WW
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 0
1
Publication Order Number:
74HCU04/D
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PIN ASSIGNMENT
A1 1
Y1 2
A2 3
Y2 4
A3 5
Y3 6
GND 7
14 VCC
13 A6
12 Y6
11 A5
10 Y5
9 A4
8 Y4
FUNCTION TABLE
Inputs
A
L
H
Outputs
Y
H
L
74HCU04
LOGIC DIAGRAM
A1 1
2 Y1
A2 3
4 Y2
5
A3
6
Y3
A4 9
11
A5
A6 13
8 Y4
10
Y5
12 Y6
Y=A
PIN 14 = VCC
PIN 7 = GND
ORDERING INFORMATION
Device
Package
Shipping†
74HCU04DR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
74HCU04DTR2G
TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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74HCU04
ÎÎMÎÎSAymXÎÎbIMolUÎÎM RÎÎATÎÎINGÎÎS ÎÎÎÎPaÎÎramÎÎeterÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎalueÎÎÎÎÎÎUnÎÎit
VCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin
±20 mA
Iout DC Output Current, per Pin
±25 mA
ICC DC Supply Current, VCC and GND Pins
±50 mA
PD Power Dissipation in Still Air
SOIC Package†
TSSOP Package†
500
450
mW
Tstg Storage Temperature
– 65 to + 150
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
TL Lead Temperature, 1 mm from case for 10 Seconds
SOIC or TSSOP Package
260
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — SOIC Package: –7mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Max Unit
VCC
Vin, Vout
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
2.0
0
– 55
−
6.0
VCC
+ 125
No
Limit
V
V
_C
ns
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