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W632GU8KB PDF даташит

Спецификация W632GU8KB изготовлена ​​​​«Winbond» и имеет функцию, называемую «32M x 8-BANKS x 8-BIT DDR3L SDRAM».

Детали детали

Номер произв W632GU8KB
Описание 32M x 8-BANKS x 8-BIT DDR3L SDRAM
Производители Winbond
логотип Winbond логотип 

30 Pages
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W632GU8KB Даташит, Описание, Даташиты
W632GU8KB
32M 8 BANKS 8 BIT DDR3L SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. BLOCK DIAGRAM ..............................................................................................................................11
8. FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality ..............................................................................................................................12
8.2 RESET and Initialization Procedure ....................................................................................................12
8.2.1
Power-up Initialization Sequence .....................................................................................12
8.2.2
Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1
Mode Register MR0 .........................................................................................................17
8.3.1.1
Burst Length, Type and Order ................................................................................17
8.3.1.2
CAS Latency...........................................................................................................18
8.3.1.3
Test Mode...............................................................................................................18
8.3.1.4
DLL Reset...............................................................................................................18
8.3.1.5
Write Recovery .......................................................................................................19
8.3.1.6
Precharge PD DLL .................................................................................................19
8.3.2
Mode Register MR1 .........................................................................................................19
8.3.2.1
DLL Enable/Disable................................................................................................20
8.3.2.2
Output Driver Impedance Control ...........................................................................20
8.3.2.3
ODT RTT Values ....................................................................................................20
8.3.2.4
Additive Latency (AL) .............................................................................................20
8.3.2.5
Write leveling ..........................................................................................................20
8.3.2.6
Output Disable........................................................................................................21
8.3.2.7
TDQS, TDQS#........................................................................................................21
8.3.3
Mode Register MR2 .........................................................................................................22
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................23
8.3.3.2
CAS Write Latency (CWL) ......................................................................................23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................23
8.3.4
Mode Register MR3 .........................................................................................................24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1
DLL onto DLL offProcedure ..........................................................................26
8.7.2
DLL offto DLL onProcedure ..........................................................................27
8.8 Input clock frequency change..............................................................................................................28
8.8.1
Frequency change during Self-Refresh............................................................................28
8.8.2
Frequency change during Precharge Power-down ..........................................................28
Publication Release Date: Jan. 20, 2015
Revision: A05
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W632GU8KB Даташит, Описание, Даташиты
W632GU8KB
8.9 Write Leveling .....................................................................................................................................30
8.9.1
DRAM setting for write leveling & DRAM termination function in that mode ....................31
8.9.2
Write Leveling Procedure.................................................................................................31
8.9.3
Write Leveling Mode Exit .................................................................................................33
8.10 Multi Purpose Register........................................................................................................................34
8.10.1
MPR Functional Description.............................................................................................35
8.10.2
MPR Register Address Definition.....................................................................................36
8.10.3
Relevant Timing Parameters............................................................................................36
8.10.4
Protocol Example .............................................................................................................36
8.11 ACTIVE Command..............................................................................................................................42
8.12 PRECHARGE Command ....................................................................................................................42
8.13 READ Operation .................................................................................................................................43
8.13.1
READ Burst Operation .....................................................................................................43
8.13.2
READ Timing Definitions..................................................................................................44
8.13.2.1
READ Timing; Clock to Data Strobe relationship....................................................45
8.13.2.2
READ Timing; Data Strobe to Data relationship .....................................................46
8.13.2.3
tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .............................................47
8.13.2.4
tRPRE Calculation..................................................................................................48
8.13.2.5
tRPST Calculation ..................................................................................................48
8.13.2.6
Burst Read Operation followed by a Precharge......................................................54
8.14 WRITE Operation................................................................................................................................56
8.14.1
DDR3L Burst Operation ...................................................................................................56
8.14.2
WRITE Timing Violations .................................................................................................56
8.14.2.1
Motivation ...............................................................................................................56
8.14.2.2
Data Setup and Hold Violations..............................................................................56
8.14.2.3
Strobe to Strobe and Strobe to Clock Violations.....................................................56
8.14.2.4
Write Timing Parameters ........................................................................................56
8.14.3
Write Data Mask...............................................................................................................57
8.14.4
tWPRE Calculation...........................................................................................................58
8.14.5
tWPST Calculation ...........................................................................................................58
8.15 Refresh Command ..............................................................................................................................65
8.16 Self-Refresh Operation .......................................................................................................................67
8.17 Power-Down Modes............................................................................................................................69
8.17.1
Power-Down Entry and Exit .............................................................................................69
8.17.2
Power-Down clarifications - Case 1 .................................................................................75
8.17.3
Power-Down clarifications - Case 2 .................................................................................75
8.17.4
Power-Down clarifications - Case 3 .................................................................................76
8.18 ZQ Calibration Commands..................................................................................................................77
8.18.1
ZQ Calibration Description ...............................................................................................77
8.18.2
ZQ Calibration Timing ......................................................................................................78
8.18.3
ZQ External Resistor Value, Tolerance, and Capacitive loading......................................78
8.19 On-Die Termination (ODT) ..................................................................................................................79
8.19.1
ODT Mode Register and ODT Truth Table ......................................................................79
8.19.2
Synchronous ODT Mode..................................................................................................80
8.19.2.1
ODT Latency and Posted ODT...............................................................................80
8.19.2.2
Timing Parameters .................................................................................................80
8.19.2.3
ODT during Reads..................................................................................................82
8.19.3
Dynamic ODT ..................................................................................................................83
8.19.3.1
Functional Description: ...........................................................................................83
Publication Release Date: Jan. 20, 2015
Revision: A05
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W632GU8KB Даташит, Описание, Даташиты
W632GU8KB
8.19.3.2
ODT Timing Diagrams ............................................................................................84
8.19.4
Asynchronous ODT Mode................................................................................................88
8.19.4.1
8.19.4.2
Synchronous to Asynchronous ODT Mode Transitions ..........................................89
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry ..89
8.19.4.3
8.19.4.4
low periods
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit.....92
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
93
9.
9.1
9.2
9.3
OPERATION MODE ...........................................................................................................................94
Command Truth Table ........................................................................................................................94
CKE Truth Table .................................................................................................................................96
Simplified State Diagram.....................................................................................................................97
10.
10.1
10.2
10.3
ELECTRICAL CHARACTERISTICS ...................................................................................................98
Absolute Maximum Ratings ................................................................................................................98
Operating Temperature Condition.......................................................................................................98
DC & AC Operating Conditions ...........................................................................................................98
10.3.1
Recommended DC Operating Conditions ........................................................................98
10.4 Input and Output Leakage Currents ....................................................................................................99
10.5 Interface Test Conditions ....................................................................................................................99
10.6 DC and AC Input Measurement Levels.............................................................................................100
10.6.1
DC and AC Input Levels for Single-Ended Command and Address Signals..................100
10.6.2
10.6.3
DC and AC Input Levels for Single-Ended Data Signals................................................100
Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ...........102
10.6.4
10.6.5
Single-ended requirements for differential signals .........................................................103
Differential Input Cross Point Voltage ............................................................................104
10.6.6
10.6.7
Slew Rate Definitions for Single-Ended Input Signals....................................................105
Slew Rate Definitions for Differential Input Signals ........................................................105
10.7 DC and AC Output Measurement Levels ..........................................................................................106
10.7.1
Output Slew Rate Definition and Requirements .............................................................106
10.7.1.1
10.7.1.2
Single Ended Output Slew Rate ...........................................................................107
Differential Output Slew Rate ...............................................................................108
10.8 34 Ohm Output Driver DC Electrical Characteristics.........................................................................109
10.8.1
Output Driver Temperature and Voltage sensitivity........................................................111
10.9 On-Die Termination (ODT) Levels and Characteristics .....................................................................112
10.9.1
ODT Levels and I-V Characteristics ...............................................................................112
10.9.2
10.9.3
ODT DC Electrical Characteristics .................................................................................113
ODT Temperature and Voltage sensitivity .....................................................................113
10.9.4
Design guide lines for RTTPU and RTTPD .......................................................................114
10.10
ODT Timing Definitions............................................................................................................115
10.10.1
10.10.2
Test Load for ODT Timings ............................................................................................115
ODT Timing Definitions ..................................................................................................115
10.11
Input/Output Capacitance ........................................................................................................119
10.12
Overshoot and Undershoot Specifications...............................................................................120
10.12.1
AC Overshoot /Undershoot Specification for Address and Control Pins: .......................120
10.12.2
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins:.........120
10.13
IDD and IDDQ Specification Parameters and Test Conditions ................................................121
10.13.1
IDD and IDDQ Measurement Conditions .......................................................................121
10.13.2
IDD Current Specifications .............................................................................................131
10.14
Clock Specification ..................................................................................................................132
10.15
Speed Bins ..............................................................................................................................133
10.15.1
DDR3L-1333 Speed Bin and Operating Conditions .......................................................133
Publication Release Date: Jan. 20, 2015
Revision: A05
-3-










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Номер в каталогеОписаниеПроизводители
W632GU8KB32M x 8-BANKS x 8-BIT DDR3L SDRAMWinbond
Winbond

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