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H5TC2G83EFR-RDA PDF даташит

Спецификация H5TC2G83EFR-RDA изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «2Gb DDR3L SDRAM».

Детали детали

Номер произв H5TC2G83EFR-RDA
Описание 2Gb DDR3L SDRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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H5TC2G83EFR-RDA Даташит, Описание, Даташиты
2Gb DDR3L SDRAM
2Gb DDR3L SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TC2G43EFR-xxA
H5TC2G83EFR-xxA
* SK hynix reserves the right to change products or specifications without notice.
Rev. 1.1 / Apr. 2013
1
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H5TC2G83EFR-RDA Даташит, Описание, Даташиты
Revision History
Revision No.
0.1
0.2
1.0
1.1
History
Initial Release
IDD5B spec modified
1.0 version release
Editorial PKG Dimension
Draft Date
Jul. 2012
Nov. 2012
Jan. 2013
Apr. 2013
Remark
Rev. 1.1 / Apr. 2013
2
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H5TC2G83EFR-RDA Даташит, Описание, Даташиты
Description
The H5TC2G43EFR-xxA and H5TC2G83EFR-xxA are a 2Gb low power Double Data Rate III (DDR3L) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density,
high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with
the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)
SK hynix 2Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling
edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling
edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling
edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• Average Refresh Cycle (Tcase of0 oC~95oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
JEDEC standard 78ball FBGA(x4/x8)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
Rev. 1.1 / Apr. 2013
3
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Номер в каталогеОписаниеПроизводители
H5TC2G83EFR-RDA2Gb DDR3L SDRAMHynix Semiconductor
Hynix Semiconductor

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