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PDF PI3VDP411LS Data sheet ( Hoja de datos )
| Número de pieza | PI3VDP411LS | |
| Descripción | Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI3VDP411LS
Features
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
•
•
•
•
Converts low-swing AC coupled differential input to
HDMI rev 1.3 compliant open-drain current steering Rx
terminated differential output
HDMI level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
Integrated 50-ohm termination resistors for AC-coupled
differential inputs.
Enable/Disable feature to turn off TMDS outputs to
enter low-power state.
Description
Pericom Semiconductor’s PI3VDP411LS provides the ability to
use a Dual-mode DP transmitter in HDMI mode. This flexibility
provides the user a choice of how to connect to their favorite
display. All signal paths accept AC coupled video signals. The
PI3VDP411LS converts this AC coupled signal into an HDMI
rev 1.3 compliant signal with proper signal swing. This conver-
stion is automatic and transparent to the user.
•
•
Output slew rate control on TMDS outputs to minimize
EMI.
Transparent operation: no re-timing or configuration
The PI3VDP411LS supports up to 2.5Gbps, which provides 12-
bits of color depth per channel, as indicated in HDMI rev 1.3.
required.
• 3.3 Power supply required.
• Integrated ESD protection to 2kV Human Body on all
I/O pins
• DDC level shifters
• Level shifter for HPD signal from HDMI/DVI
connector
• Integrated pull-down on HPD_sink input guarantees
"input low" when no display is plugged in
07-0198
Pin Configuration
GND
IN_D1-
IN_D1+
VCC3V
IN_D2-
IN_D2+
GND
IN_D3-
IN_D3+
VCC3V
IN_D4-
IN_D4+
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 21
41 20
42 48-pin QFN Pinout 19
43 18
44 17
45 16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
GND
OUT_D1-
OUT_D1+
VCC3V
OUT_D2-
OUT_D2+
GND
OUT_D3-
OUT_D3+
VCC3V
OUT_D4-
OUT_D4+
1
PS8913A
08/29/07
1 page  
PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
Pin Name
OUT_D2+
OUT_D2–
OUT_D1+
OUT_D1–
HPD_SINK
HPD_SOURCE
SCL_SOURCE
SDA_SOURCE
SCL_SINK
SDA_SINK
DDC_EN
VCC3V
OC_2 (1)
(REXT)
Type
TMDS Differential output
TMDS Differential output
TMDS Differential output
TMDS Differential output
Description
HDMI 1.3 compliant TMDS output. OUT_D2+ makes
a differential output signal with OUT_D2–.
HDMI 1.3 compliant TMDS output. OUT_D2– makes
a differential output signal with OUT_D2+.
HDMI 1.3 compliant TMDS output. OUT_D1+ makes
a differential output signal with OUT_D1–.
HDMI 1.3 compliant TMDS output. OUT_D1– makes
a differential output signal with OUT_D1+.
5V tolerance single-ended input
Low Frequency, 0V to 5V (nominal) input signal. This
signal comes from the HDMI connector. Voltage High
indicates "plugged" state; voltage low indicated
"unplugged". HPD_SINK is pulled down by an
integrated 100K ohm pulldown resistor.
3.3V single-ended output
HPD_SOURCE: 0V to 3.3V (nominal) output signal.
This is level-shiftedversion of the HPD_SINK signal.
Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external termina-
DDC I/O
tion to 3.3V. Connected to SCL_SINK through volt-
age-limiting intergrated NMOS passgate.
Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external termination
DDC I/O
to 3.3V. Connected to SDA_SINK through voltage-
limiting intergrated NMOS passgate.
Single-ended 5V open-drain
DDC I/O
5V DDC Clock I/O. Pulled up by external termination
to 5V. Connected to SCL_SOURCE through voltage-
limiting integrated NMOS passgate.
Single-ended 5V open-drain
DDC I/O
5V DDC Data I/O. Pulled up by external termination
to 5V. Connected to SDA_SOURCE through voltage-
limiting integrated NMOS passgate.
5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter
gates. (May be implemented as a bias voltage connec-
tion to the DDC pass gates themselves.)
DDC_EN
Passgate
0V Disabled
3.3V
Enabled
3.3V DC Supply
3.3V single-ended control input
3.3V ± 10%
Acceptable connections to OC_1 (REXT) pin are: Re-
sistor to GND; Resistor to 3.3V; NC. (Resistor should
be 0-ohm).
Note:
1) internal 100Kohm pull-up
07-0198
5
PS8913A
08/29/07
5 Page 
Packaging Mechanical: 48-Pin, TQFN (ZD)
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PI3VDP411LS
Digital Video Level Shifter from AC coupled
digital video input to a DVI/HDMI transmitter
(
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.OTES
!LL DIMENSIONS ARE IN MILLIMETERS ANGLES IN DEGREES
2EF *%$%# -/
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4HERMAL 6IA $IAMETER 2ECOMMENDED ^MM
4HERMAL 6IA 0ITCH 2ECOMMENDED MM
"ILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG
AS WELL AS THE TERMINALS
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! %##!$ ! $ ''!&$
DATE: 03/10/06
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD48)
DOCUMENT CONTROL #: PD-2045
REVISION: A
Ordering Information
Ordering Code
PI3VDP411LSZDE
Package Code
ZD
Package Description
48-pin Pb-free & Green, TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
07-0198
11
PS8913A
08/29/07
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet PI3VDP411LS.PDF ] | |
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