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PDF MS90C386B Data sheet ( Hoja de datos )
| Número de pieza | MS90C386B | |
| Descripción | 24bits COLOR LVDS Receiver | |
| Fabricantes | Ruimeng Technology | |
| Logotipo |  |
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MS90C386B
MS90C386B
——+3.3V 175MHz 24bits COLOR LVDS Receiver
General Description
The MS90C386B receiver is designed to support pixel data transmission
between Host and Flat Panel Display from NTSC up to SXGA resolutions. The
MS90C386B converts the LVDS data streams back into 28bits of CMOS/TTL
data with the choice of the rising edge or falling edge clock for the convenience
with a variety of LCD panel controllers. At a transmit clock frequency of
175Mhz, 24bits of GRB data and 4bits of timing and control data
(HSYNC,VSYCN,DE,CNTL) are transmitted at an effective rate of 1225Mbps
per LVDS channel. Using a 175MHz clock, the data throughput is
612.5Mbytes/sec.
Features
Clock range：20-175MHz
Narrow bus reduces cable size
Single 3.3V supply
Power-down Mode
Supports VGA、SVGA、XGA、SXGA
Up to 4.9Gbps throughput
Up to 612.5Megabytes/sec bandwidth
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
TSSOP56 Package
Hangzhou Ruimeng Technology Co.,LTD
Http: www.relmon.com
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1 page  
MS90C386B
TRH
TTL Data Hold from CLKOUT
1.0
ns
TTLH TTL Low to High Transition
23
ns
Time
TTHL TTL High to Low Transition
Time
23
ns
TRCD RCLK to CLKOUT Delay
7.0 ns
TRDP5 Position 0
175MHz
-0.4
0 +0.4
ns
TRDP6 Position 1
T/7-0.4 T/7 T/7+0.4
ns
TRDP0 Position 2
2T/7-0.4 2T/7 2T/7+0.4 ns
TRDP1 Position 3
3T/7-0.4 3T/7 3T/7+0.4 ns
TRDP2 Position 4
4T/7-0.4 4T/7 4T/7+0.4 ns
TRDP3 Position 5
5T/7-0.4 5T/7 5T/7+0.4 ns
TRDP4 Position 6
6T/7-0.4 6T/7 6T/7+0.4 ns
TTPLLS
PLL Set
-
- 10
ms
AC Timing Diagram
FIGURE 1.Test Pattern “Worst Case Pattern”
FIGURE 2.Test Pattern “16 Grayscale Test Pattern”
Hangzhou Ruimeng Technology Co.,LTD
Http: www.relmon.com
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5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MS90C386B.PDF ] | |
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