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PDF AK4421A Data sheet ( Hoja de datos )
| Número de pieza | AK4421A | |
| Descripción | 192kHz 24-Bit Stereo DAC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK4421A]
AK4421A
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4421A is 3.3V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4421A delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4421A integrates a combination of
switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock
jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer
audio applications, such as portable A/V players, set-top boxes, and digital televisions. The AK4421A is
offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Soft mute
I/F format: 24-Bit MSB justified or I2S
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
THD+N: -92dB
Dynamic Range: 102dB
Automatic Power-on Reset Circuit
Power supply: +3.0 ∼ +3.6V
Ta = -20 to 85°C
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
SMUTE
DIF
Control
Interface
LRCK
BICK
SDTI
Audio
Data
Interface
Clock
Divider
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
Charge
Pump
CP CN VEE VSS2 CVDD
2.2 μ
2.2μ
VDD
DZF
VSS1
AOUTL
AOUTR
MS1086-E-01
-1-
2009/09
1 page  
[AK4421A]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +3.3V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥10kΩ, unless otherwise specified)
Parameter
min typ max
Units
Resolution
24 Bits
THD+N
fs=44.1kHz, BW=20kHz
-92 -84 dB
fs=96kHz, BW=40kHz
-92 - dB
fs=192kHz, BW=40kHz
-92 - dB
Dynamic Range (-60dBFS with A-weighted, Note 6)
96 102
dB
S/N (A-weighted, Note 7)
96 102
dB
Interchannel Isolation (1kHz)
90 100
dB
Interchannel Gain Mismatch
0.2 0.5 dB
DC Accuracy
DC Offset (at output pin)
-40 0 40 mV
Gain Drift
100 - ppm/°C
Output Voltage (Note 8)
1.85 2.0 2.15 Vrms
Load Capacitance (Note 9)
25 pF
Load Resistance
10 kΩ
Power Supplies
Power Supply Current: (Note 10)
Normal Operation (fs≤96kHz)
Normal Operation (fs=192kHz)
Power-Down Mode (Note 11)
14 21 mA
16 24 mA
10 100 μA
Note 5. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 6. 98dB for 16-bit input data
Note 7. S/N does not depend on input data size.
Note 8. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD:
AOUT (typ.@0dB) = 2Vrms × VDD/3.3.
Note 9. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 10. The current into VDD and CVDD.
Note 11. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD. (The SMUTE and
DIF pins are not included)
MS1086-E-01
-5-
2009/09
5 Page 
[AK4421A]
■ Zero Detect Function
When the input data for both channels are continuously zero for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF
pin immediately returns to “L” if the input data for both channels are not zero.
■ Analog Output Block
The internal negative power supply generation circuit (Figure 5) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4421A to output an audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative
power generation circuit (Figure 5) needs 2.2uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4421A is placed in reset mode automatically and the analog
outputs settle to VSS (0V, typ).
AK4421A
CVDD
Charge
Pump
Negative Power
CP CN VSS2
(+)
2.2uF Ca
Cb
(+)
VEE
2.2u F
AK4421A
Figure 5. Negative Power Generation Circuit
AOUTR
(AOUTL)
0V
2V rm s
Figure 6. Audio Signal Output
MS1086-E-01
- 11 -
2009/09
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AK4421A.PDF ] | |
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