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PDF MPC5642A Data sheet ( Hoja de datos )
| Número de pieza | MPC5642A | |
| Descripción | Microcontroller | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
MPC5642A
Rev. 3.2, 12/2014
MPC5642A Microcontroller
Datasheet
This is the MPC5642A Datasheet set consisting of the following files:
• MPC5642A Datasheet Addendum (MPC5642A_AD), Rev. 1
• MPC5642A Datasheet (MPC5642A), Rev. 3.1
© Freescale Semiconductor, Inc., 2014. All rights reserved.
1 page  
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5642A
Rev. 3.1, 06/2012
Qorivva MPC5642A
Microcontroller Data Sheet
MPC5642A
• 150 MHz e200z4 Power Architecture core
– Variable length instruction encoding (VLE)
– Superscalar architecture with 2 execution units
– Up to 2 integer or floating point instructions per cycle
– Up to 4 multiply and accumulate operations per cycle
• Memory organization
– 2 MB on-chip flash memory with ECC and
read-while-write (RWW)
– 128 KB on-chip SRAM with standby functionality (32
KB) and ECC
– 8 KB instruction cache (with line locking), configurable
as 2- or 4-way
– 14 + 3 KB eTPU code and data RAM
– 4 4 crossbar switch (XBAR)
– 24-entry MMU
• Fail Safe Protection
– 16-entry Memory Protection Unit (MPU)
– CRC unit with 3 submodules
– Junction temperature sensor
• Interrupt
– Configurable interrupt controller (INTC) with
non-maskable interrupt (NMI)
– 64-channel eDMA
• Serial channels
– 3 eSCI modules
– 3 DSPI modules (2 of which support downstream Micro
Second Channel [MSC])
– 3 FlexCAN modules with 64 message buffers each
– 1 FlexRay module (V2.1) up to 10 Mbit/s w/dual or
single channel, 128 message objects, ECC
• 1 eMIOS
– 24 unified channels
• 1 eTPU2 (second generation eTPU)
—32 standard channels
208 MAPBGA
(17 x 17 mm)
176 LQFP
(24 × 24 mm)
324 TEPBGA
(23 × 23 mm)
– 1 reaction module (6 channels with 3 outputs per
channel)
• 2 enhanced queued analog-to-digital converters (eQADCs)
– Forty 12-bit input channels (multiplexed on 2 ADCs);
expandable to 56 channels with external multiplexers
– 6 command queues
– Trigger and DMA support
– 688 ns minimum conversion time
• On-chip CAN/SCI Bootstrap loader with Boot Assist
Module (BAM)
• Nexus: Class 3+ for core; Class 1 for eTPU
• JTAG (5-pin)
• Development Trigger Semaphore (DTS)
– EVTO pin for communication with external tool
• Clock generation
– On-chip 4–40 MHz main oscillator
– On-chip FMPLL (frequency-modulated phase-locked
loop)
• Up to 112 general purpose I/O lines
– Individually programmable as input, output or special
function
– Programmable threshold (hysteresis)
• Power reduction modes: slow, stop, and standby
• Flexible supply scheme
– 5 V single supply with external ballast
– Multiple external supply: 5 V, 3.3 V, and 1.2 V
© Freescale Semiconductor, Inc., 2009, 2010, 2012. All rights reserved.
5 Page 
Introduction
Table 2. MPC5642A series block summary
Block
Boot assist module (BAM)
Calibration bus interface
Controller area network (FlexCAN)
Crossbar switch (XBAR)
Cyclic redundancy check (CRC)
Deserial serial peripheral interface (DSPI)
e200z4 core
Enhanced direct memory access (eDMA)
Enhanced modular input-output system
(eMIOS)
Enhanced queued analog-to-digital
converter (eQADC)
Enhanced serial communication interface
(eSCI)
Enhanced time processor unit (eTPU2)
Error Correction Status Module (ECSM)
Flash memory
FlexRay
Frequency-modulated phase-locked loop
(FMPLL)
Interrupt controller (INTC)
JTAG controller
Memory protection unit (MPU)
Nexus port controller (NPC)
Periodic interrupt timer (PIT)
Reaction Module (REACM)
Function
Block of read-only memory containing executable code that searches
for user-supplied boot code and, if none is found, executes the BAM
boot code resident in device ROM
Transfers data across the crossbar switch to/from peripherals attached
to the calibration system connector
Supports the standard CAN communications protocol
Internal busmaster
CRC checksum generator
Provides a synchronous serial interface for communication with
external devices
Executes programs and interrupt handlers
Performs complex data movements with minimal intervention from the
core.
Provides the functionality to generate or measure events
Provides accurate and fast conversions for a wide range of
applications
Provides asynchronous serial communication capability with
peripheral devices and other microcontroller units
Second-generation co-processor processes real-time input events,
performs output waveform generation, and accesses shared data
without host intervention
The Error Correction Status Module supports a number of
miscellaneous control functions for the platform, and includes registers
for capturing information on platform memory errors if error-correcting
codes (ECC) are implemented
Provides storage for program code, constants, and variables
Provides high-speed distributed control for advanced automotive
applications
Generates high-speed system clocks and supports programmable
frequency modulation
Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode
Provides hardware access control for all memory references
generated
Provides real-time development support capabilities in compliance
with the IEEE-ISTO 5001-2010 standard
Produces periodic interrupts and triggers
Works in conjunction with the eQADC and eTPU2 to increase system
performance by removing the CPU from the current control loop.
Freescale Semiconductor
MPC5642A Microcontroller Data Sheet, Rev. 3.1
7
11 Page | ||
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| PDF Descargar | [ Datasheet MPC5642A.PDF ] | |
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