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PDF CY7C1382BV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1382BV25 | |
| Descripción | 512K x 36 / 1 Mb x 18 Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
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1CY7C1 380B V25
PRELIMINARY
CY7C1380BV25
CY7C1382BV25
512K x 36 / 1 Mb x 18 Pipelined SRAM
Features
• Fast clock speed: 200,166, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns
• Optimal for depth expansion
• 2.5V (±5%) Operation
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed WRITE CYCLE
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1382BV25 and CY7C1380BV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and Burst
Mode Control (MODE). The data (DQa,b,c,d) and the data par-
ity (DQPa,b,c,d) outputs, enabled by OE, are also asynchro-
nous.
DQa,b,c,d and DQPa,b,c,d apply to CY7C1380BV25 and DQa,b
and DQPa,b apply to CY7C1382BV25. a, b, c, d each are of 8
bits wide in the case of DQ and 1 bit wide in the case of DP.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQc and DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
All inputs and outputs of the CY7C1380BV25 and the
CY7C1382BV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
200 MHz 166 MHz 150 MHz 133 MHz
Maximum Access Time (ns)
3.0 3.4 3.8 4.2
Maximum Operating Current (mA)
Commercial
280 230 190 160
Maximum CMOS Standby Current (mA)
30 30 30 30
Shaded areas contain advance information.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 5, 2001
1 page  
PRELIMINARY
CY7C1380BV25
CY7C1382BV25
Pin Definitions
Name
A0
A1
A
BWa
BWb
BWc
BWd
GW
BWE
CLK
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
CE1 Input-
Synchronous
CE2 Input-
Synchronous
CE3 Input-
Synchronous
OE Input-
Asynchronous
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
ADSC
Input-
Synchronous
MODE
ZZ
DQa, DQPa
DQb, DQPb
DQc, DQPc
DQd, DQPd
Input-
Static
Input-
Asynchronous
I/O-
Synchronous
TDO
TDI
JTAG serial
output
Synchronous
JTAG serial
input
Synchronous
Description
Address Inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and
CE3 are sampled active. A[1:0] feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless of
the values on BWa,b,c,d and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ig-
nored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE3 to select/deselect the device. (TQFP Only)
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE1 and CE2 to select/deselect the device. (TQFP Only)
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH,
I/O pins are three-stated, and act as input data pins. OE is masked during the
first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP
is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When
tied to VDDQ or left floating selects interleaved burst sequence. This is a strap
pin and should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are
placed in a three-state condition.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK
(BGA Only).
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA
Only).
5
5 Page 
PRELIMINARY
CY7C1380BV25
CY7C1382BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380BV25/CY7C1382BV25 incorporates a serial
boundary scan Test Access Port (TAP) in the FBGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Control-
ler State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is con-
nected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruc-
tion register. This register is loaded when it is placed between
the TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow
for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long regis-
ter, and the x18 configuration has a yy-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data or control signals into the
11
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C1382BV25.PDF ] | |
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