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PDF MC10E451 Data sheet ( Hoja de datos )

Número de pieza MC10E451
Descripción 6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK
Fabricantes Motorola Semiconductors 
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No Preview Available ! MC10E451 Hoja de datos, Descripción, Manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
6ĆBit D Register Differential
Data and Clock
The MC10E/100E451 contains six D-type flip-flops with single-ended
outputs and differential data inputs. The common clock input is also
differential. The registers are triggered by a positive transition of the
positive clock (CLK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to LOW.
The VBB output is intended for use as a reference voltage for
single-ended reception of ECL signals to that device only. When using for
this purpose, it is recommended that VBB is decoupled to VCC via a
0.01µF capacitor.
The differential input structures are clamped so that the inputs of
unused registers can be left open without upsetting the bias network of
the device. The clamping action will assert the D and the CLK sides of the
inputs. Because of the edge triggered flip-flop nature of the device
simultaneously opening both the clock and data inputs will result in an
output which reaches an unidentified but valid state. Note that the input
clamps only operate when both inputs fall to 2.5V below VCC.
Differential Inputs: Data and Clock
VBB Output
1100MHz Min. Toggle Frequency
Asynchronous Master Reset
Extended 100E VEE Range of – 4.2V to – 5.46V
75kInput Pulldown Resistors
D5 D5 D4 D4 D3 D3 VCCO
25 24 23 22 21 20 19
CLK 26
18 Q5
VBB 27
17 Q4
CLK 28
16 VCC
VEE 1
MR 2
NC 3
Pinout: 28-Lead PLCC
(Top View)
15 Q3
14 VCCO
13 Q2
D0 4
12 Q1
5 6 7 8 9 10 11
D0 D1 D1 D2 D2 VCCO Q0
* All VCC and VCCO pins are tied together on the die.
PIN NAMES
Pin Function
D0 – D5
D0 – D5
CLK
CLK
MR
VBB
Q0 – Q5
+Data Input
– Data Input
+Clock Input
– Clock Input
Master Reset Input
VBB Output
Data Outputs
12/93
© Motorola, Inc. 1996
2–1
MC10E451
MC100E451
6-BIT D REGISTER
DIFFERENTIAL
DATA AND CLOCK
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
LOGIC DIAGRAM
D0
D0
D Q0
R
D1
D1
D Q1
R
D2 D Q2
D2
R
D3
D3
D Q3
R
D4
D4
D Q4
R
D5
D5
D Q5
R
CLK
CLK
MR
VBB
REV 2

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