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PDF ADP1974 Data sheet ( Hoja de datos )
| Número de pieza | ADP1974 | |
| Descripción | Synchronous PWM Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Bidirectional, Synchronous PWM Controller
for Battery Test and Formation
ADP1974
FEATURES
GENERAL DESCRIPTION
Input voltage range: 6 V to 60 V
On-board 5 V linear regulator
Buck/charge or boost/discharge mode
High PWM linearity with internal 4 V p-p PWM ramp voltage
FAULT and COMP input compatible with AD8450/AD8451
Programmable dead time control
Adjustable frequency from 50 kHz to 300 kHz
Synchronization output or input with adjustable phase shift
Programmable maximum duty cycle
Programmable soft start
Peak hiccup current-limit protection
Pin-compatible with ADP1972 (asynchronous version)
TSD protection
16-lead TSSOP
APPLICATIONS
Single and multicell battery formation and testing
High efficiency battery test systems with recycle capability
Battery conditioning (charging and discharging) systems
Compatible with AD8450/AD8451 constant voltage (CV) and
constant current (CC) analog front end error amplifier
The ADP1974 is a constant frequency, voltage mode, synchronous,
pulse-width modulation (PWM) controller for bidirectional dc-to-
dc applications. The ADP1974 is designed for use in battery testing,
formation, and conditioning applications with an external, high
voltage field effect transistor (FET) half bridge driver, and an
external control device such as the AD8450/AD8451. The device
operates as a buck converter in battery charge mode and as a boost
converter in discharge mode to recycle energy to the input bus.
The ADP1974 high voltage VIN supply pin can withstand a
maximum operating voltage of 60 V and reduces the need for
additional system supply voltages. The ADP1974 has integrated
features such as precision enable, internal and external
synchronization control with programmable phase shift,
programmable maximum duty cycle, dead time control, and peak
hiccup current-limit protection. Additional protection features
include soft start to limit input inrush current during startup,
precision enable, and thermal shutdown (TSD). The ADP1974
also has a COMP pin to provide external control of the PWM
duty cycle and a FAULT pin that can disable the DH and DL
outputs. These functions are compatible with the AD8450/AD8451
analog front-end (AFE) error amplifiers.
The ADP1974 is available in a 16-lead TSSOP package and is
pin-compatible with the ADP1972.
TYPICAL APPLICATION CIRCUIT
BATTERY CHARGER SYSTEM CONTROL
+24V
VOLTAGE CURRENT
CHARGE/
SETPOINT SETPOINT DISCHARGE
ON/OFF
LOOP
COMPENSATION
ISET MODE
VCTRL
VSET
FAULT
AD8450
BVP0 BVN0 ISVN ISVP
+––+
VIN
VREG
SYNC
SCFG
EN ADP1974
MODE
DH
COMP
FAULT
FREQ
DMAX
GND
DL
CL
DT
SS
HV
MOSFET
DRIVER
ADuM7223
+24V RECYLCING DC BUS
NOTES
1. THE AD8450 AND ADuM7223 ARE SIMPLIFIED REPRESENTATIONS.
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP1974
Data Sheet
Parameter
PRECISION ENABLE LOGIC (EN)
Maximum EN Pin Voltage
EN Threshold Rising
EN Threshold Falling
EN Pin Current
MODE LOGIC
Maximum MODE Pin Voltage
MODE Threshold Rising
MODE Threshold Falling
CURRENT LIMIT (CL)
Set Current
Buck CL Threshold
Buck Negative Current Threshold
Boost CL Threshold
Hiccup Detect Time
Hiccup Off Time
VREG
LDO Regulator Output Voltage
Guaranteed Output Current
Load Regulation
FAULT
Maximum FAULT Pin Voltage
FAULT Threshold Rising
FAULT Threshold Falling
FAULT Pin Current
PWM DRIVE LOGIC SIGNALS (DH/DL)
DL Drive Voltage
DH Drive Voltage
DL and DH Sink Resistance
DL and DH Source Resistance
DL and DH Pull-Down Resistor
THERMAL SHUTDOWN (TSD)
TSD Threshold Rising
TSD Threshold Falling
Symbol Test Conditions/Comments
Min Typ Max Unit
VEN = 5 V, internal pull down
60 V
1.25 1.4 V
1.1 1.22
V
0.32 2
μA
5.5 V
1.20 1.5 V
0.7 1.05
V
ICL
VCL (BUCK)
VNC (BUCK)
VCL (BOOST)
VVREG
IOUT (MAX)
VCL = 0 V
RFREQ = 100 kΩ, 500 consecutive clock pulses
RFREQ = 100 kΩ, 500 consecutive clock pulses
EN = high
VIN = 6 V to 60 V, no external load
VIN = 6 V, external load
VIN = 6 V, IOUT = 0 mA to 5 mA
18 20
250 300
400 450
450 500
5.2
5.2
21 μA
350 mV
500 mV
550 mV
ms
ms
4.9 5
4.9 5
5.1 V
5 mA
5.1 V
VFAULT
60 V
1.2 1.5 V
0.7 1.05
V
VFAULT = 5 V, internal 8.5 MΩ pull-down resistor
0.49 2
μA
VDL No load
VDH No load
IDL = 10 mA
IDL = 10 mA
VREG
V
VREG
V
1.2 2.4 Ω
1.4 2.6 Ω
0.5 1
1.5 MΩ
150 °C
135 °C
1 The DMAX and SCFG current matching specification is calculated by taking the absolute value of the difference between the measured ISCFG and IDMAX currents, dividing
them by the 11 μA typical value, and multiplying this answer by 100.
DMAX
and
SCFG
Current
Matching
(%)
I
SCFG
I DMAX
100
11 μA
Rev. 0 | Page 4 of 19
5 Page 
ADP1974
Data Sheet
THEORY OF OPERATION
VIN
CIN
4.7µF
VIN VREG
CVREG
1µF
EN VREG
VREG = 5V
FAULT
AD8450
SYNC
8.5MΩ
1MΩ
UVLO TSD BAND GAP
VBG = 1.252V
SYNC
DETECT
FREQ
RFREQ
SCFG
DMAX
VREG
IFREQ
OSCILLATOR
IFREQ
CONFIG
DETECT
VREG
IFREQ
CDMAX
RDMAX
COMP
AD8450
SS
CSS
VREG
ISS
5µA
SS DISCHARGE
1kΩ
4V
MODE
MODE
SELECT
DRIVE
LOGIC
MODE
SELECT
500mV
300mV
DH
1MΩ
DL
1MΩ
5V 15V
24V
M1
EXTERNAL
DRIVER
M2
L
VREG
ICL
20µA
CL
RCL
20kΩ
GND
RS
AGND PGND
450mV
VREG
VREG VREG
10µA
IDT
20µA
1.64pF
DT
RDT
CDT
ADP1974
VOUT
COUT
Figure 20. Internal Block Diagram
The ADP1974 is a constant frequency, voltage mode, synchronous,
PWM controller for bidirectional dc-to-dc applications. The
ADP1974 is designed to be used with an external, high voltage
FET half bridge driver, such as the ADuM7223, and an external
error amplifier AFE device, such as the AD8450/AD8451, to
implement a battery testing, charging, and discharging system.
The ADP1974 has a high input voltage range, multiple externally
programmed control pins, and integrated safety features. In
buck mode, the device charges a battery and delivers energy
from the input power source to the output. In boost mode, the
device discharges a battery and delivers energy from the battery
to the input. In both modes, the ADP1974 operates as a
synchronous controller for maximum efficiency.
SUPPLY PINS
The ADP1974 has two voltage supply pins, VIN and VREG.
The VIN pin operates from an external supply that ranges from
6 V to 60 V and is the supply voltage for the internal linear
regulator of the ADP1974. Bypass the VIN pin to ground with a
4.7 μF or greater ceramic capacitor.
The VREG pin is the output of the internal linear regulator. The
internal regulator generates the 5 V (typical) rail that is used
internally to bias the control circuitry and can be used externally
as a pull-up voltage for the MODE, SYNC, DMAX, and FAULT
pins. Bypass the VREG pin to ground with a 1 μF ceramic
capacitor. VREG is disabled when EN is low and is active as
long as VIN is above the internal UVLO (5.71 V typical) and
EN is high.
Rev. 0 | Page 10 of 19
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADP1974.PDF ] | |
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