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PDF CY2X0147 Data sheet ( Hoja de datos )
| Número de pieza | CY2X0147 | |
| Descripción | Low-Jitter LVPECL Crystal Oscillator | |
| Fabricantes | Cypress Semiconductor | |
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CY2X014
CY2X0147
Low-Jitter LVPECL Crystal Oscillator
Low-Jitter LVPECL Crystal Oscillator
Features
■ Low-jitter crystal oscillator (XO)
■ Less than 1-ps typical root mean square (RMS) phase jitter
■ Low-voltage positive emitter coupled logic (LVPECL) output
■ Output frequency from 50 MHz to 690 MHz
■ Factory-configured or field-programmable
■ Integrated phase-locked loop (PLL)
■ Can be configured as four different devices
■ Supply voltage: 3.3 V or 2.5 V
■ Pb-free chip carrier (LCC): 5.0 mm × 3.2 mm for CY2X014 and
7.0 mm × 5.0 mm for CY2X0147
■ Commercial and industrial temperature ranges
Functional Description
The CY2X014/CY2X0147 device is a high-performance and
high-frequency XO. The device uses a Cypress proprietary
low-noise PLL to synthesize the frequency from an integrated
crystal.
The CY2X014/CY2X0147 device is available as a
factory-configured device or as a field-programmable device.
Factory-configured devices are configured for general use or
they can be customer-specific. The same CY2X014/CY2X0147
can be configured as four different device types as mentioned in
the Logic Block Diagram.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-88287 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 13, 2016
1 page  
CY2X014
CY2X0147
Functional Description
Device Type 1
Device Type 1 is a simple crystal oscillator with one output
frequency. Pin 1 can be programmed either as OE or PD#. The
OE function is used to enable or disable the CLK output whereas
the PD# function places the device in a low-power state.
Device Type 2
Device Type 2 has an I2C bus serial interface [1], which is used
to change the output frequency.
The CY2X014/CY2X0147 device is configured for four
frequencies. At power-on, the four configurations are
transparently loaded into an internal volatile memory which, in
turn, controls the PLL. The user can switch between the four
frequencies through the I2C bus. The user can also configure the
CY2X014/CY2X0147 with new output frequencies by shifting
new data into the internal memory.
Frequency margining is a common application for this feature.
One frequency is used for the standard operating mode of the
device, while additional frequencies are available for margin
testing, either during product development or in-system
manufacturing test.
Note that all configuration changes made using I2C are
temporary and are lost when power is removed from the device.
At power-on, the device returns to its original state.
The configuration for a particular frequency is stored in a 6-byte
block of memory, known as a word. The CY2X014/CY2X0147
device has four such words, labeled ‘Frequency Word 0’ through
‘Frequency Word 3’. An additional register byte contains a 2-bit
field, which selects one of the four frequency words. By writing
to this select byte, the user can switch back and forth between
the four programmed frequencies. The select byte can be
configured to select any of the four frequency words at power-on.
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new
frequency.Glitches and runt pulses are possible, and time must
be allowed for the PLL to relock.
If more than four frequencies are needed, the I2C bus can be
used to change any of the four frequency words. When writing
frequency words through I2C, the users should not change the
currently selected word. Instead, write one of the three
unselected words before changing the select byte to select that
new word.
Figure 2 shows how the frequency words are arranged and
selected.
Figure 2. Frequency Words
Register
Address
10h – 15h
16h – 1Bh
1Ch – 21h
22h – 27h
Frequency Word 0
Frequency Word 1
Frequency Word 2
Frequency Word 3
40h Select Byte
Bits [1:0]
00
01
10
11
Sel
Control
PLL
Device Type 3
The FS0 and FS1 pins select between four different output
frequencies, as shown in Table 1. Frequency margining is a
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in-system manufacturing test.
Table 1. Frequency Select
FS1 FS0
Output Frequency
0 0 Frequency 0
0 1 Frequency 1
1 0 Frequency 2
1 1 Frequency 3
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Device Type 4
Device Type 4 is a voltage-controlled crystal oscillator. It has a
control voltage pin, VIN, which is an analog input used to adjust
the output frequency. The nominal output frequency is defined
when VIN = VDD,NOM/2. Increasing the voltage on VIN
increases the output frequency, while decreasing the voltage on
VIN decreases the output frequency. Any voltage between VSS
and VDD is allowed on VIN. The voltage or frequency slope is
very linear over most of the control voltage range.
Note
1.
The serial interface is I2C Bus compliant
setup time, and output hold time.
with
the
following
exceptions:
SDA
input
leakage
current,
SDA
input
capacitance,
SDA,
and
SCLK
are
clamped
to
VDD,
Document Number: 001-88287 Rev. *E
Page 5 of 21
5 Page 
CY2X014
CY2X0147
Absolute Maximum Conditions
Parameter
VDD
VIN[3]
TS
TJ
ESDHBM
ΘJA[4]
Description
Supply voltage
Input voltage, DC
Temperature, storage
Temperature, junction
Electrostatic discharge (ESD)
protection human body model
(HBM)
Thermal resistance, junction to
ambient
Condition
Relative to VSS
Non operating
JEDEC Std 22-A114-B
0 m/s airflow
Min
–0.5
–0.5
–55
–40
2000
Max
4.4
VDD + 0.5
135
135
–
Unit
V
V
°C
°C
V
64 °C /
W
Operating Conditions
Parameter
Description
Min Typ Max Unit
VDD 3.3 V supply voltage range
2.5 V supply voltage range
3.0 3.3 3.6 V
2.375
2.5
2.625
V
TPU
Power-up time for VDD to reach minimum specified voltage (power
0.05
–
500 ms
ramp is monotonic)
TA Ambient temperature (commercial)
Ambient temperature (industrial)
0–
–40 –
70 °C
85 °C
Notes
3. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
4. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 × 114 × 1.6 mm and has 4 layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document Number: 001-88287 Rev. *E
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet CY2X0147.PDF ] | |
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