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PDF SSM2537 Data sheet ( Hoja de datos )
| Número de pieza | SSM2537 | |
| Descripción | Mono 2.7 W Class-D Audio Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
PDM Digital Input, Mono
2.7 W Class-D Audio Amplifier
SSM2537
FEATURES
architecture enables extremely low real-world power consumption
Filterless digital Class-D amplifier
Pulse density modulation (PDM) digital input interface
2.7 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion plus noise (THD + N)
Available in 9-ball, 1.2 mm × 1.2 mm, 0.4 mm pitch WLCSP
93% efficiency into 8 Ω at full scale
Output noise: 25 µV rms at 3.6 V, A-weighted
from digital audio sources with excellent audio performance. Using
the SSM2537, audio can be transmitted digitally to the audio
amplifier, significantly reducing the effect of noise sources such
as GSM interference or other digital signals on the transmitted
audio. The SSM2537 is capable of delivering 2.7 W of continu-
ous output power with <1% THD + N driving a 4 Ω load from a
5.0 V supply.
THD + N: 0.005% at 1 kHz, 100 mW output power
The SSM2537 features a high efficiency, low noise modulation
PSRR: 80 dB at 217 Hz, with dither input
scheme that requires no external LC output filters. The closed-loop,
Quiescent power consumption: 5.1 mW
three-level modulator design retains the benefits of an all-digital
(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 µH load)
Pop-and-click suppression
Configurable with PDM pattern inputs
Short-circuit and thermal protection with autorecovery
Smart power-down when PDM stop condition or no clock
input detected
64 × fS or 128 × fS operation supporting 3 MHz and 6 MHz clocks
DC blocking high-pass filter and static input dc protection
User-selectable ultralow EMI emissions and low latency modes
Power-on reset (POR)
Minimal external passive components
APPLICATIONS
amplifier, yet enables very good PSRR and audio performance. The
modulation continues to provide high efficiency even at low output
power and has an SNR of 102 dB PDM input. Spread-spectrum
pulse density modulation is used to provide lower EMI-radiated
emissions compared with other Class-D architectures.
The SSM2537 has a four-state gain and sample frequency selection
pin that can select two different gain settings, optimized for 3.6 V
and 5 V operation. This same pin controls the internal digital fil-
tering and clocking, which can be set for a 64 × fS or 128 × fS input
sample rate to support both 3 MHz and 6 MHz PDM clock rates.
The SSM2537 has a micropower shutdown mode with a typical
shutdown current of 1.6 µA for both power supplies. Shutdown is
Mobile handsets
enabled automatically by gating input clock and data signals. A
GENERAL DESCRIPTION
The SSM2537 is a PDM digital input Class-D power amplifier
that offers higher performance than existing DAC plus Class-D
solutions. The SSM2537 is ideal for power sensitive applications
where system noise can corrupt the small analog signal sent to
the amplifier, such as mobile phones and portable media players.
The SSM2537 combines an audio digital-to-analog converter
(DAC), a power amplifier, and a PDM digital interface on a single
chip. The integrated DAC plus analog sigma-delta (Σ-Δ) modulator
standby mode can be entered by applying a designated PDM stop
condition sequence. The device also includes pop-and-click sup-
pression circuitry. This suppression circuitry minimizes voltage
glitches at the output when entering or leaving the low power
state, reducing audible noises on activation and deactivation.
The SSM2537 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.2 mm ×
1.2 mm wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
VDD
PVDD PGND
PDAT
PCLK
POWER-ON
RESET
CLOCKING POWER
CONTROL
INPUT
INTERFACE
FILTERING/
DAC
Σ-Δ
CLASS-D
MODULATOR
SSM2537
FULL-BRIDGE
POWER STAGE
OUT+
OUT–
GAIN_FS
Figure 1.
LRSEL
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
SSM2537
Parameter
Supply Current, Modulator
Standby Current
Shutdown Current
NOISE PERFORMANCE
Output Voltage Noise
Signal-to-Noise Ratio
Symbol
IVDD
Test Conditions/Comments
Dither input, 8 Ω + 33 µH load
VDD = 1.8 V, fS = 64×
VDD = 1.8 V, fS = 128×
VDD = 1.8 V, fS = 64×
VDD = 1.8 V, fS = 128×
VDD = 1.8 V
en Dither input, A-weighted
PVDD = 3.6 V, fS = 64×
PVDD = 3.6 V, fS = 128×
PVDD = 5.0 V, fS = 64×
PVDD = 5.0 V, fS = 128×
SNR PO = 1.4 W, PVDD = 5.0 V, RL = 8 Ω,
A-weighted
fS = 64×
fS = 128×
Min Typ
0.3
0.6
37
68
1.6
25
27
33
30
102
102
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
INPUT SPECIFICATIONS
Input Voltage High
PCLK, PDAT, LRSEL Pins
Input Voltage Low
PCLK, PDAT, LRSEL Pins
Input Leakage Current High
PDAT, LRSEL Pins
PCLK Pin
Input Leakage Current Low
PDAT, LRSEL Pins
PCLK Pin
Input Capacitance
Symbol Min
VIH
0.7 × VDD
VIL
−0.3
IIH
IIL
Typ
Max Unit
3.6
0.3 × VDD
1
3
1
3
5
V
V
V
µA
µA
µA
µA
pF
Data Sheet
Max Unit
mA
mA
µA
µA
µA
µV
µV
µV
µV
dB
dB
Rev. 0 | Page 4 of 16
5 Page 
SSM2537
100
RL = 8Ω + 33µH
PVDD = 2.5V
fS = 128×
10
1
0.1
0.25W
0.01
0.001
10
0.0625W
100
0.125W
1k 10k
100k
FREQUENCY (Hz)
Figure 16. THD + N vs. Frequency, PVDD = 2.5 V, RL = 8 Ω, fS = 128×
100 RL = 4Ω + 15µH
PVDD = 5V
fS = 128×
10
1
0.1 2W
0.01
0.5W
1W
0.001
10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 17. THD + N vs. Frequency, PVDD = 5 V, RL = 4 Ω, fS = 128×
100
RL = 4Ω + 15µH
PVDD = 3.6V
fS = 128×
10
1
0.1 1W
0.01
0.001
10
0.25W
100
0.5W
1k
10k
100k
FREQUENCY (Hz)
Figure 18. THD + N vs. Frequency, PVDD = 3.6 V, RL = 4 Ω, fS = 128×
Data Sheet
100
RL = 4Ω + 15µH
PVDD = 2.5V
fS = 128×
10
1
0.1
0.5W
0.01
0.25W
0.125W
0.001
10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 19. THD + N vs. Frequency, PVDD = 2.5 V, RL = 4 Ω, fS = 128×
2.0
fS = 64×
1.9
1.8
1.7
1.6
1.5 8Ω + 33µH
1.4
4Ω + 15µH
1.3
1.2
NO LOAD
1.1
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Figure 20. Quiescent Current vs. Supply Voltage, fS = 64×
2.0
fS = 128×
1.9
1.8
1.7
1.6
1.5 8Ω + 33µH
1.4
1.3
NO LOAD
1.2
4Ω + 15µH
1.1
1.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
Figure 21. Quiescent Current vs. Supply Voltage, fS = 128×
Rev. 0 | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet SSM2537.PDF ] | |
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