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PDF SiC531 Data sheet ( Hoja de datos )
| Número de pieza | SiC531 | |
| Descripción | Integrated Power Stage | |
| Fabricantes | Vishay | |
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SiC531, SiC531A
Vishay Siliconix
30 A VRPower® Integrated Power Stage
DESCRIPTION
The SiC531 and SiC531A are integrated power stage
solutions optimized for synchronous buck applications
to offer high current, high efficiency, and high power
density performance. Packaged in Vishay’s proprietary
4.5 mm x 3.5 mm MLP package, SiC531 and SiC531A
enable voltage regulator designs to deliver up to 30 A
continuous current per phase.
The internal power MOSFETs utilize Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC531 and SiC531A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, and zero current detection to
improve light load efficiency. The drivers are also
compatible with a wide range of PWM controllers, support
tri-state PWM, and 3.3 V (SiC531A) / 5 V (SiC531) PWM
logic.
FEATURES
• Thermally enhanced PowerPAK® MLP4535-22L
package
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 30 A continuous current, 35 A at 10 ms peak
current
• High efficiency performance
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 19 V input stage
• 3.3 V (SiC531A) / 5 V (SiC531) PWM logic with tri-state and
hold-off
• Zero current detect control for light load efficiency
improvement
• Low PWM propagation delay (< 20 ns)
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and memory
• Intel IMVP-8 VRPower delivery
-VCORE, VGRAPHICS, VSYSTEM AGENT Skylake, Kabylake platforms
-VCCGI for Apollo Lake platforms
• Up to 18 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5 V VIN
PWM
controller
VCIN
ZCD_EN#
PWM
Gate
driver
BOOT
PHASE
VSWH
VOUT
Fig. 1 - SiC531 and SiC531A Typical Application Diagram
S15-2799-Rev. A, 30-Nov-15
1
Document Number: 65999
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 page  
www.vishay.com
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low-side is turned OFF and the high-side is
turned ON. When PWM input is driven below VPWM_TH_F the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC531 and
SiC531A to pull the PWM input into the tri-state region (see
definition of PWM logic and Tri-State, fig. 4). If the PWM
input stays in this region for the Tri-state Hold-Off Period,
tTSHO, both high-side and low-side MOSFETs are turned
OFF. The function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC531A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC531 thresholds are compatible with 5 V logic.
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is logic low and PWM signal switches
low, GL is forced ON (after normal BBM time). During this
time, it is under control of the ZCD (zero crossing detect)
comparator. If, after the internal blanking delay, the inductor
current becomes zero, the low-side is turned OFF. This
improves light load efficiency by avoiding discharge of
output capacitors. If PWM enters tri-state, then device will
go into normal tri-state mode after tri-state delay. The GL
output will be turned OFF regardless of Inductor current, this
is an alternative method of improving light load efficiency by
reducing switching losses.
Voltage Input (VIN)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
SiC531, SiC531A
Vishay Siliconix
Ground Connections (CGND and PGND)
PGND (power ground) should be externally connected to
CGND (signal ground). The layout of the printed circuit board
should be such that the inductance separating CGND and
PGND is minimized. Transient differences due to inductance
effects between these two pins should not exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV, VCIN)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
Bootstrap Circuit (BOOT)
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Shoot-Through Protection and Adaptive Dead Time
The SiC531 and SiC531A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high-side and low-side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning ON from tuning ON until the other
MOSFET's gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
OFF, before the other can be turned ON. This feature helps
to adjust dead time as gate transitions change with respect
to output current and temperature.
Under Voltage Lockout (UVLO)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC531 and
SiC531A also incorporate logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.
S15-2799-Rev. A, 30-Nov-15
5
Document Number: 65999
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
5 Page 
www.vishay.com
Step 5: Signal Routing
AGND
AGND
SiC531, SiC531A
Vishay Siliconix
Step 7: Ground Connection
AGND
VSWH
PGND
PGND
1. Route the PWM and ZCD_EN# signal traces out of the
top left corner next to pin 1.
2. The PWM signal is an important signal, both signal and
return traces should not cross any power nodes on any
layer.
3. It is best to “shield” these traces from power switching
nodes, e.g. VSWH, with a GND island to improve signal
integrity.
4. GL (pin 19) has been connected with GL pad (pin 24)
internally.
Step 6: Adding Thermal Relief Vias
AGND
VIN
PGND
VSWH
VIN Plane
PGND Plane
1. Thermal relief vias can be added on the VIN and AGND
pads to utilize inner layers for high-current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be placed on VIN plane and PGND plane.
3. VSWH pad is a noise source, it is not recommended to
place vias on this pad.
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Consult with the
assembly house for guidelines.
1. It is recommended to make a single connection between
AGND and PGND which can be made on the top layer.
2. It is recommended to make the entire first inner layer
(below top layer) the ground plane and separate them
into AGND and PGND planes.
3. These ground planes provide shielding between noise
sources on top layer and signal traces on bottom layer.
S15-2799-Rev. A, 30-Nov-15
11
Document Number: 65999
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet SiC531.PDF ] | |
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