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PDF AIC1570 Data sheet ( Hoja de datos )
| Número de pieza | AIC1570 | |
| Descripción | 5-bit DAC/ Synchronous PWM Power Regulator with LDO and Linear Controller | |
| Fabricantes | Analog Intergrations Corporation | |
| Logotipo |  |
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AIC1570
5-bit DAC, Synchronous PWM Power Regulator
with LDO and Linear Controller
FEATURES
Compatible with HIP6018.
Provides 3 Regulated Voltages for Micro-
processor Core, Clock and GTL Power.
Simple Voltage-Mode PWM Control.
Dual N-Channel MOSFET Synchronous Driver.
Operates from +3.3V, +5V and +12V Inputs.
Fast Transient Response.
Full 0% to 100% Duty Ratios.
±1.0% Output Voltage for VCORE and ±2.0%
Output Voltage Reference for VCLK and VGTL.
TTL Compatible 5-bit Digital-to-Analog Core
Output Voltage Selection. Range from 1.3V to
3.5V.
0.1V Steps from 2.1V to 3.5V.
0.05V Steps from 1.3V to 2.05V.
Adjustable Current Limit without External Sense
Resistor.
Microprocessor Core Voltage Protection against
Shorted MOSFET.
Power Good Output Voltage Monitor.
Over-Voltage and Over-Current Fault Monitors.
200KHz Free-Running Oscillator Programmable
up to 350KHz.
APPLICATIONS
Full Motherboard Power Regulation for
Computers.
DESCRIPTION
The AIC1570 combines a synchronous voltage
mode controller with a low dropout linear regulator
and a linear controller as well as the monitoring and
protection functions in this chip. The PWM
controller regulates the microprocessor core
voltage with a synchronous rectified buck converter.
The linear controller regulates power for the GTL
bus and the linear regulator provides power for the
clock driver circuit.
An integrated 5 bit D/A converter that adjusts the
core PWM output voltage from 2.1V to 3.5V in 0.1V
increments and from 1.3V to 2.05V in 0.05V
increments. The linear regulator uses an internal
driver device to provide 2.5V±2.5%. The linear
controller drives with an external N-channel
MOSEFET to provide 1.5V±2.5%.
This chip monitors all the output voltages. Power
Good signal is issued when the core voltage is
within ±10% of the DAC setting and the other levels
are above their under-voltage levels. Over-voltage
protection for the core output uses the lower N-
channel MOSFET to prevent output voltage above
115% of the DAC setting.
The PWM over-current function monitors the output
current by using the voltage drop across the upper
MOSFET’s RDS(on), eliminating the need for a
current sensing resistor.
DS-1570-00
www.analog.com.tw
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
UGATE
UGATE
AIC1570
LGATE
LGATE
FIG.1 The gate drive waveforms
60
CUGATE=CLGATE=CGATE
50 VCC=12V
40
CGATE=5000pF
30
CGATE=2000pF
20
10 CGATE=660pF
0
100 150 200 250 300 350 400
Switching Frequency (KHz)
FIG. 2 Bias Supply Current VS. Frequency
10000
1000
RT Pull Up to +12V
100
RT Pull Down to GND
10
1
100
150
200 250
300 350
Switching Frequency (KHz)
400
450
FIG. 3 RT Resistance VS. Frequency
SS (2V/div)
PGOOD (5V/div)
VOUT1 (1V/div)
VOUT2 (1V/div)
VOUT3 (1V/div)
SS
VDAC=3.5V
VDAC=2V
VDAC=1.3V
FIG.4 Soft Start Interval with 3 Outputs and PGOOD
FIG. 5 Soft Start Initiates PWM Output
5
5 Page 
AIC1570
LUV
OC1
0.2V
SS
3.6V
OV
OVER CURRENT
LATCH
SQ
INHIBIT
R
+
S
COUNTER
R
FAULT LATCH
S VCC
+
POR
RQ
FAULT
Fig. 10 Simplified Schematic of Fault Logic
A simplified schematic is shown in figure 10. An
over-voltage detected on VSEN immediately sets
the fault latch. A sequence of three over-current
fault signals also sets the fault latch. An under-
voltage event on either linear output (FB2 or FB3)
is ignored until the soft-start interval. Cycling the
bias input voltage (+12V) off then on reset the
counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM
MOSFET (Q1) causes VOUT1 to increase. When
the output exceed the over-voltage threshold of
115% of DACOUT, the FAULT pin is set to fault
latch and turns Q2 on as required in order to
regulate VOUT1 to 115% of DACOUT. The fault
latch raises the FAULT pin close to VCC
potential.
A separate over-voltage circuit provides
protection during the initial application of power.
For voltage on VCC pin below the power-on reset
(and above 4V), should VSEN exceed 0.7V, the
lower MOSFET (Q2) is driven on as needed to
regulate VOUT1 to 0.7V.
Over-Current Protection
All outputs are protected against excessive over-
current. The PWM controller uses upper
MOSFET’s on-resistance, RDS(ON) to monitor the
current for protection against shorted outputs.
The linear regulator monitors the current limit in
excess of 500mA. Additionally, both the linear
regulator and controller monitor FB2 and FB3 for
under-voltage to protect against excessive
current.
When the voltage across Q1 (ID•RDS(ON)) exceeds
the level (200µA•ROCSET), this signal inhibit all
outputs. Discharge soft-start capacitor (Css) with
10µA current sink, and increments the counter.
Css recharges and initiates a soft-start cycle
again until the counter increments to 3. This sets
the fault latch to disable all outputs. Fig. 6
illustrates the over-current protection until an
over load on OUT1.
Should excessive current cause FB2 or FB3 to
fall below the linear under-voltage threshold, the
LUV signal sets the over-current latch if Css is
fully charged. Cycling the bias input power off
then on reset the counter and the fault latch.
The over-current function for PWM controller will
trip at a peak inductor current (IPEAK) determined
by:
IPEAK
=
IOCSET × ROCSET
RDS(ON)
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AIC1570.PDF ] | |
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