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PDF AK4528 Data sheet ( Hoja de datos )
| Número de pieza | AK4528 | |
| Descripción | High Performance 24-Bit 96kHz Audio CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK4528]
AK4528
High Performance 24Bit 96kHz Audio CODEC
GENERAL DESCRIPTION
The AK4528 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an
Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced
Multi Bit architecture and achieves low out-band noise and high jitter tolerance by use of SCF (switched
capacitor filter) techniques.
FEATURES
• 24bit 2ch ADC
- 64x Oversampling
- Full differential Inputs
- S/(N+D): 94dB
- Dynamic Range, S/N: 108dB
- Digital HPF for offset cancellation
- I/F format: MSB justified or I2S
• 24bit 2ch DAC
- 128x Oversampling
- 24bit 8 times Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB
- SCF
- Differential Outputs
- S/(N+D): 94dB
- Dynamic Range, S/N: 110dB
- De-emphasis for 32kHz, 44.1kHz and 48kHz sampling
- Output DATT with –72dB att
- Soft Mute
- I/F format: MSB justified, LSB justified or I2S
• High Jitter Tolerance
• 3-wire Serial Interface for Volume Control
• Master Clock
- 256fs/384fs/512fs/768fs/1024fs
• 5V operation
• 3V Power Supply Pin for 3V I/F
• Small 28pin SSOP package
MS0011-E-03
-1-
2013/03
1 page  
[AK4528]
ABSOLUTE MAXIMUM RATINGS
(AGND=DGND=0V; Note 1)
Parameter
Symbol
min
Power Supplies: Analog
VA −0.3
Digital
VD −0.3
Output Buffer
VT −0.3
VD−VA
VDA
-
Input Current, Any Pin Except Supplies
IIN -
Analog Input Voltage
VINA
−0.3
Digital Input Voltage
VIND
−0.3
Ambient Temperature (powered applied)
Ta −40
Storage Temperature
Tstg −65
max
6.0
6.0
6.0
0.3
±10
VA+0.3
VA+0.3
85
150
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Unit
V
V
V
V
mA
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS
(AGND= DGND=0V; Note 1)
Parameter
Symbol
min typ
Power Supplies Analog
VA 4.75 5.0
Digital
VD 4.75 5.0
Output Buffer
VT 2.7 3.0
Voltage Reference
VREF
3.0 -
max
5.25
VA
VD
VA
Note:1. All voltages with respect to ground.
2. VA and VD should be powered at the same time or VA should be powered earlier than VD.
The power up sequence between VA and VT, or VD and VT is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Unit
V
V
V
V
MS0011-E-03
-5-
2013/03
5 Page 
[AK4528]
OPERATION OVERVIEW
System Clock Input
The external clocks, which are required to AK4528, are MCLK, BICK and LRCK. MCLK should be synchronized with
LRCK but the phase is not critical. The frequency of MCLK is set by CMODE, CKS0-1 and DFS bits in serial mode, or
by CKS0-1, DFS pins in parallel mode (see Table 2 and 3). The CKS0-1 and DFS pin should be changed during the PDN
pin = “L”. The CMODE, CKS0-1 and DFS bits are changed during RSTADN = RSTDAN = “0”.
External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4528 is in normal operation mode
(PDN = “H” and at least one of ADC and DAC is in normal operation mode). If these clocks are not provided, the
AK4528 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are
not present, the AK4528 should be in the power-down mode (PDN = “L” or set both ADC and DAC power down mode
by the register).
CMODE bit CKS1 bit CKS0 bit
0 00
0 01
0 10
1 00
1 01
MCLK
Normal Speed
(DFS bit = “0”)
256fs
512fs
1024fs
384fs
768fs
MCLK
Double Speed
(DFS bit = “1”)
N/A
256fs
512fs
N/A
384fs
Default
Table 1. Master Clock Frequency Select in Serial Mode
CKS1 pin CKS0 pin
LL
LH
HL
HH
MCLK
Normal Speed
(DFS pin = “L”)
256fs
512fs
384fs
1024fs
MCLK
Double Speed
(DFS pin = “H”)
N/A
256fs
N/A
512fs
Table 2. Master Clock Frequency Select in Parallel Mode
MCLK
Normal Speed
(DFS = “0”)
256fs
512fs
1024fs
384fs
768fs
fs=44.1kHz fs=48kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK
Double Speed
(DFS = “1”)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz fs=96kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
Table 3. Master Clock Frequencies example
Note. Do not set any mode which is not described in Table1-3.
MS0011-E-03
- 11 -
2013/03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4528.PDF ] | |
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