PDF AD8320 Data sheet ( Hoja de datos )

Número de pieza	AD8320
Descripción	Serial Digital Controlled Variable Gain Line Driver
Fabricantes	Analog Devices
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No Preview Available ! a Serial Digital Controlled Variable Gain Line Driver AD8320 FEATURES 8-Bit Serial Gain Control V/V/LSB Linear Gain Response 36 dB Gain Range ؎0.20 dB Gain Accuracy Upper Bandwidth: 150 MHz 22 dBm 1 dB Compression Point (75 ⍀) Drives Low Distortion Signals into 75 ⍀ Load: –57 dBc SFDR at 42 MHz and 12 dBm Out –46 dBc SFDR at 42 MHz and 18 dBm Out Single Supply Operation from 5 V to 12 V Maintains 75 ⍀ Output Impedance Power-Up and Power-Down Condition Supports SPI Input Control Standard APPLICATIONS Coaxial Cable Driver HFC Cable Telephony Systems HFC High Speed Data Modems Interactive Set-Top Boxes PC Plug-In Modems Interfaces with AD9853 I2C Controlled Digital Modulator High Performance Digitally Controlled Variable Gain Block VREF VIN FUNCTIONAL BLOCK DIAGRAM VCC GND REFERENCE AD8320 INV. ATTENUATOR CORE PWR AMP VOUT REVERSE AMP BUF. DATA LATCH DATA SHIFT REGISTER POWER- DOWN/ SWITCH INTER. PD DATEN CLK SDATA DESCRIPTION The AD8320 is a digitally controlled variable gain amplifier optimized for coaxial line driving applications. An 8-bit serial word determines the desired output gain over a 36 dB range (256 gain levels). The AD8320 provides linear gain response. The AD8320 is made up of a digitally controlled variable at- tenuator of 0 dB to –36 dB, which is preceded by a low noise, fixed gain buffer and followed by a low distortion high power amplifier. The AD8320 has a 220 Ω input impedance and ac- cepts a single-ended input signal with a specified analog input level of up to 0.310 V p-p. The output is specified for driving a 75 Ω load, such as coaxial cable, although the AD8320 is ca- pable of driving other loads. Distortion performance of –57 dBc is achieved with an output level up to 12 dBm (3.1 V p-p) at 42 MHz, while –46 dBc distortion is achieved with an output level up to 18 dBm (6.2 V p-p). A key performance and cost advantage of the AD8320 results from the ability to maintain a constant 75 Ω output impedance during power-up and power-down conditions. This eliminates the need for external 75 Ω back-termination, resulting in twice the effective output voltage when compared to a standard opera- tional amplifier. Additionally, the on-chip 75 Ω termination results in low glitch output during power-down and power-up transitions, eliminating the need for an external switch. The AD8320 is packaged in a 20-lead SOIC and operates from a single +5 V through +12 V supply and has an operational temperature range of –40°C to +85°C. ؊20 ؊30 PO = 18dBm ؊40 ؊50 PO = 8dBm ؊60 PO = 12dBm ؊70 PO = 4dBm ؊80 1 10 FREQUENCY – MHz 100 Figure 1. Worst Harmonic Distortion vs. Frequency for Various Output Levels at VCC = 12 V REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 1 page 0.3 VCC = 12V F = 10MHz 0.2 0.1 T = +25؇C 0 ؊0.1 T = ؊40؇C T = +85؇C ؊0.2 ؊0.3 0 64 128 192 GAIN CONTROL – Decimal 256 Figure 4. Gain Error vs. Gain Control at Various Temperatures Typical Performance Characteristics–AD8320 0.6 VCC = 12V 0.3 T = +25؇C 0 ؊0.3 ؊0.6 ؊0.9 10MHz 42MHz 65MHz ؊1.2 0 64 128 192 GAIN CONTROL – Decimal 256 Figure 5. Gain Error vs. Gain Control at Various Frequencies 0.45 F = 10MHz 0.30 T = +25؇C 0.15 0 VCC = 12V ؊0.15 ؊0.30 VCC = 5V ؊0.45 0 64 128 192 GAIN CONTROL – Decimal 256 Figure 6. Gain Error vs. Gain Control at Different Supply Voltages 30 255D VCC = 5V 20 170D 85D 10 0 01D ؊10 00D ؊20 100k 1M 10M 100M FREQUENCY – Hz Figure 7. AC Response 1G 30 255D 20 170D 85D 10 VCC = 12V 0 ؊10 01D 00D ؊20 100k 1M 10M 100M FREQUENCY – Hz Figure 8. AC Response 1G ؊20 ؊30 ؊40 MAX GAIN PD = 0V ؊50 ؊60 ؊70 VCC = 5V, PIN = ؊14dBm ؊80 ؊90 ؊100 100k VCC = 12V, PIN = ؊8dBm 1M 10M 100M FREQUENCY – Hz 1G Figure 9. Input Signal Feedthrough vs. Frequency 80 F = 10MHz 75 VCC = 12V 70 65 60 55 +85؇C +25؇C ؊40؇C 50 45 40 0 64 128 192 256 GAIN CONTROL – Decimal Figure 10. Output Referred Noise vs. Gain Control at Various Temperatures 80 75 F = 10MHz 70 65 VCC = 12V 60 55 VCC = 5V 50 45 40 0 64 128 192 256 GAIN CONTROL – Decimal Figure 11. Output Referred Noise vs. Gain Control at Different Supply Voltages 90 80 MAX GAIN, VCC = 12V 70 MAX GAIN, VCC = 5V 60 MIN GAIN, VCC = 12V 50 MIN GAIN, VCC = 5V 40 30 100k 1M 10M FREQUENCY – Hz 100M Figure 12. Output Referred Noise vs. Frequency REV. 0 –5– 5 Page AD8320 Basic Connection Figure 45 shows the basic schematic for operating the AD8320. Because the amplifier operates from a single supply, the input signal must be ac-coupled using a 0.1 µF capacitor. The input pin has a bias level of about 1.9 V. This bias level is available on the VREF pin (Pin 18) and can be used to externally bias signals if dc-coupling is desired. Under all conditions, a 0.1 µF decoupling capacitor must be connected to the VREF pin. If the VREF volt- age is to be used externally, it should be buffered first. The VIN pin of the AD8320 (Pin 19) has an input impedance of 220 Ω. Typically, in video applications, 75 Ω termination is favored. As a result, an external shunt resistance (R1) to ground of 115 Ω is required to create an overall input impedance of 75 Ω. If 50 Ω termination is required, a 64.9 Ω shunt resistor should be used. Note, to avoid dc loading of the VIN pin, the ac-coupling capacitor should be placed between the input pin and the shunt resistor as shown in Figure 45. On the output side, the VOUT pin also has a dc bias level. In this case the bias level is midway between the supply voltage and ground. The output signal must therefore be ac-coupled before being applied to the load. The dc bias voltage is available on the VOCM pin (Pin 5) and can be used in dc-coupled applications. This node must be decoupled to ground using a 0.1 µF capaci- tor. If the VOCM voltage is to be used externally, it should be buffered. Since the AD8320 has a dynamic output impedance of 75 Ω, no external back termination resistor is required. If the output signal is being evaluated on 50 Ω test equipment such as a spec- trum analyzer, a 75 Ω to 50 Ω adapter (commonly called a pad) should be used to maintain a properly matched circuit. Varying the Gain The gain of the AD8320 can be varied over a range of 36 dB, from –10 dB to +26 dB, by varying the 8-bit gain setting word. The timing diagram for AD8320’s serial interface is shown in Figure 43. The write cycle to the device is initiated by the falling edge of DATEN. This is followed by eight clock pulses that clock in the control word. Because the clock signal is level triggered, data is effectively clocked on the falling edge of CLK. After the control word has been clocked in, the DATEN line goes back high, allowing the gain to be updated (this takes about 30 ns). The relationship between gain and control word is given by the equation: Gain (V/V) = 0.077 × Code + 0.316 where code is the decimal equivalent of the gain control word (0 to 255). The gain in dB is given by the equation: Gain (dB) = 20 log10 (0.077 × Code + 0.316) The digital interface also contains an asynchronous power-down mode. The normally high PD line can be pulled low at any time. This turns off the output signal after 45 ns, and reduces the quiescent current to between 25 mA and 32 mA (depending upon the power supply voltage). In this mode, the programmed gain is maintained. Clock Line Feedthrough Clock feedthrough results in a 5 mV p-p signal appearing super- imposed on the output signal (see Figure 32). If this impinges upon the dynamic range of the application, the clock signal should be noncontinuous, i.e., should only be turned on for eight cycles during programming. Power Supply and Decoupling The AD8320 should be powered with a good quality (i.e., low noise) single supply of between +5 V and +12 V. In order to achieve an output power level of +18 dBm (6.2 V p-p) into VCC +5V TO +12V C7 10␮F C12 0.1␮F INPUT R1* 115⍀ C1 0.1␮F *FOR A 75⍀ INPUT IMPEDANCE C6 0.1␮F C5 0.1␮F C4 0.1␮F C2 0.1␮F C11 0.1␮F C3 0.1␮F VCC VCC VCC VCC VREF VIN REFERENCE AD8320 ATTENUATOR CORE VCC GND BYP VOUT C10 0.1␮F VOCM TO DIPLEXER RIN = 75⍀ C8 0.1␮F DATEN CLK DATA LATCH DATA SHIFT REGISTER POWER- DOWN / SWITCH INTER. PD SDATA GND GND GND GND GND REV. 0 CLK SDATA DATEN PD Figure 45. Basic Connection –11– 11 Page

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