PDF CS7410 Data sheet ( Hoja de datos )

Número de pieza	CS7410
Descripción	CD/MP3/WMA Audio Controller
Fabricantes	Cirrus Logic
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No Preview Available ! CS7410 CD/MP3/WMA Audio Controller Features l Super on-chip Integration for low cost and low count bill of materials l 32-Bit RISC Processor performs audio decode and system management functions l 16-bit DSP for audio special effects l 80 Kbytes internal SRAM, and 256 Kbytes internal ROM l Interfaces to external SDRAM or EDO DRAM (for shock protection), and to external ROM/FLASH (for custom program storage) l CD serial interface with advanced pattern matching and software error handling l Integrated DAC functionality l Simultaneous 4 channels PCM audio output and IEC-958 output. l Large number of GPIO pins for servo control, key scan, LCD control, etc. l Three serial control/status ports l Sophisticated clock management and low power consumption l Supports ISO9660 and multi-session write methods l Low power 0.18 micron technology l 100-pin MQFP package l 100-pin LQFP package Description The CS7410 is a true system-on-a-chip for the CD- based digital audio market. With a powerful RISC pro- cessor, one DSP, integrated audio ∆Σ modulator, large internal SRAM and program ROM, and glueless inter- face to popular CD chip sets, the CS7410 is a complete single chip low-power programmable audio decoder. This powerful architecture is easily capable of MP3, WMA, and other future audio formats. The CS7410’s flexible architecture and low power consumption make it an ideal low-cost solution for a wide range of player ap- plications. For portable audio systems, the memory interface can be used to add DRAM or SRAM for Elec- tronic Shock Protection (ESP). A flexible set of interfaces are available for end-user I/O such as a keypad and LCD control for use in mass market CD players, boom boxes, and shelf-top systems. ORDERING INFORMATION CS7410-CM 0° to 70° C 100-pin MQFP CS7410-CQ 0° to 70° C 100-pin LQFP RISC-32 Instruction Cache Data Cache CPU MAC CD Interface Control FIFO PLL DSP-16 Instruction Cache X,Y Data memory CPU / MAC System Miscellaneous Clock Control Register Bank Timers Get Bits Audio Interface ∆Σ Modulator PCM Out IEC-958 80 KB Internal SRAM External Interface 2-Wire Debug Interface 3/4 Wire Serial Programmable I/O PWM Out Memory Controller ROM/SRAM Control Mini DMA Flash Control DRAM Control 256 KB Internal ROM Preliminary Product Information Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2002 (All Rights Reserved) JUL ‘02 DS553PP1 1 1 page CS7410 1. CHARACTERISTICS AND SPECIFICATIONS 1.1 AC AND DC PARAMETRIC SPECIFICATIONS (AGND, DGND=0V, all voltages with respect to 0V) 1.1.1 Absolute Maximum Rating Symbol Description Min. Max. Unit VDDIO VDDCORE VI II IO TSOL Power Supply Voltage on I/O ring Power Supply Voltage on core logic and PLL Digital Input Applied Voltage (power applied) Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature -0.5 4.6 Volts -0.5 2.5 Volts -0.5 5.5 Volts -10 10 mA -50 50 mA 260 oC TVSOL Vapor Phase Soldering Temperature 235 oC TSTOR Storage Temperature (no power applied) -40 125 oC TAMB Ambient Temperature (power applied) 0 70 oC PTOT Power consumption 1W CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS7410 devices operate at the settings described in the next ta- ble. 1.1.2 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage, IO Supply Voltage, core and PLL Ambient Temperature (power applied) Symbol VDD VDD TAMB 1.1.3 Electrical Specifications (TA = 0 to 70 oC) Parameter Power Supply Supply Current, IO Supply Current, core and PLL Symbol Conditions IDD Normal Operating IDD Normal Operating Min Typ Max Units 3.0 3.3 3.6 Volts 1.62 1.8V 1.98 0 25 70 Volts oC Min Typ Max Units 13 mA 70 mA DS553PP1 5 5 Page 1.1.4.2 Serial Interface CS7410 Symbol tclk_per tDMs tDMh tDSs tCMs tDSh Description Clock period Master-mode data setup Master-mode data hold Slave-mode data setup Master chip select to clock setup Slave mode data hold Min 66 28 28 15 28 0 Typ Table 2. Serial Interface Characterization Data Max Unit ns ns ns ns ns ns SER2_CLK (CPOL=0) SER2_CLK (CPOL=1) SER2_DO (master) SER2_DI (slave) SER2_CS tCMs tDMs MSB tDSs MSB tclk_per tDMh tDSh Figure 6. Serial Interface Timing Diagram LSB LSB DS553PP1 11 11 Page

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