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PDF ALD500ASC Data sheet ( Hoja de datos )
| Número de pieza | ALD500ASC | |
| Descripción | PRECISION INTEGRATING ANALOG PROCESSOR | |
| Fabricantes | Advanced Linear Devices | |
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ADVANCED
LINEAR
DEVICES, INC.
ALD500AU/ALD500A/ALD500
PRECISION INTEGRATING ANALOG PROCESSOR
APPLICATIONS
• 4 1/2 digits to 5 1/2 digits plus sign measurements
• Precision analog signal processor
• Precision sensor interface
• High accuracy DC measurement functions
• Portable battery operated instruments
• Computer peripheral
• PCMCIA
GENERAL DESCRIPTION
The ALD500AU/ALD500A/ALD500 are integrating dual slope analog
processors, designed to operate on ±5V power supplies for building
precision analog-to-digital converters. The ALD500AU/ALD500A/
ALD500 feature specifications suitable for 18 bit/17 bit/16 bit resolution
conversion, respectively. Together with three capacitors, one resistor,
a precision voltage reference, and a digital controller, a precision
Analog to Digital converter with auto zero can be implemented. The
digital controller can be implemented by an external microcontroller,
under either hardware (fixed logic) or software control. For ultra high
resolution applications, up to 23 bit conversion can be implemented with
an appropriate digital controller and software.
The ALD500 series of analog processors accept differential inputs and
the external digital controller first counts the number of pulses at a fixed
clock rate that a capacitor requires to integrate against an unknown
analog input voltage, then counts the number of pulses required to
deintegrate the capacitor against a known reference voltage. This
unknown analog voltage can then be converted by the microcontroller
to a digital word, which is translated into a high resolution number,
representing an accurate reading. This reading, when ratioed against
the reference voltage, yields an accurate, absolute voltage measurement
reading.
The ALD500 analog processors consist of on-chip digital control circuitry
to accept control inputs, integrating buffer amplifiers, analog switches,
and voltage comparators. It functions in four operating modes, or
phases, namely auto zero, integrate, deintegrate, and integrator zero
phases. At the end of a conversion, the comparator output goes from
high to low when the integrator crosses zero during deintegration.
ALD500 analog processors also provide direct logic interface to CMOS
logic families.
ORDERING INFORMATION
0°C to +70°C
Operating Temperature Range *
0°C to +70°C
0°C to +70°C
16-Pin
Plastic Pin
Package
16-Pin
Small Outline
Package (SOIC)
16-Pin Wide Body
Small Outline
Package (SOIC)
ALD500PC (16 bit)
ALD500APC (17 bit)
ALD500AUPC (18 bit)
ALD500SC (16 bit)
ALD500ASC (17 bit)
ALD500AUSC (18 bit)
* Contact factory for industrial temperature range
ALD500SWC (16 bit)
ALD500ASWC (17 bit)
ALD500AUSWC (18 bit)
BENEFITS
• Wide dynamic signal range
• Very high noise immunity
• Low cost, simple functionality
• Automatic compensation and cancellation of
error sources
• Easy to use to acquire true 18 bit,17 bit, or
16 bit conversion and noise performance
• Inherently linear and stable with temperature
and component variations
FEATURES
• Resolution up to 18 bits plus sign bit
and over-range bit
• Accuracy independent of input source
impedances
• High input impedance of 1012 Ω
• Inherently filters and integrates any
external noise spikes
• Differential analog input
• Wide bipolar analog input voltage
range ±3.5V
• Automatic zero offset compensation
• Low linearity error - as low as 0.002%
• Fast zero-crossing comparator - 1µs
• Low power dissipation - 6mW typical
• Automatic internal polarity detection
• Low input current - 2pA typical
• Microprocessor controlled conversion
• Optional digital control from a microcon-
troller, an ASIC, or a dedicated digital circuit
• Flexible conversion speed versus resolution
trade-off
PIN CONFIGURATION
ALD500
CINT
V-
CAZ
BUF
AGND
C-REF
C+REF
V-REF
1
2
3
4
5
6
7
8
16 V+
15 DGND
14 COUT
13 B
12 A
11 V+IN
10 V-IN
9 V+REF
PC, SC, SWC PACKAGE
Rev. 1.02 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286
http://www.aldinc.com
1 page  
DC ELECTRICAL CHARACTERISTICS
TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47µf
Parameter
Supply Current
500AU
500A
500
Symbol Min Typ Max Min Typ Max Min Typ Max
Unit Test Conditions
IS
0.6 1.0
0.6 1.0
0.6 1.0 mA
V+ = 5V , A =1,B=1
Power Dissipation
PD
10 10
10 mW VSUPPLY = ±5V
Positive Supply Range V+S
4.5
5.5 4.5
5.5 4.5
5.5 V
Note 4
Negative Supply Range V-S
-4.5
-5.5 -4.5
-5.5 -4.5
-5.5 V
Note 4
Comparator Logic 1,
Output High
Comparator Logic 0,
Output Low
Logic 1, Input High
Voltage
Logic 0, Input Low
Voltage
Logic Input Current
Comparator Delay
VOH
4
4
4 V ISOURCE = 400µA
VOL
0.4 0.4
0.4 V
ISINK = 1.1mA
VIH 3.5
3.5
3.5
V
VIL
11
1V
IL 0.01
tD 1
0.01
1
0.01 µA
1 µsec Note 5
NOTES:
1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., VINT ~= 4V, VIN = 2.0V Full Scale
Resolution = VINT /integrate time/clock period
2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.
3. Rollover Error also depends on CINT, CREF, CAZ characteristics.
4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V.
5. Recommended selection of clock periods of one of the following:
t clk = 0.27µsec, 0.54µsec, or 1.09µsec
which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
Figure 3. ALD500 TIMING DIAGRAM
1 Conversion Cycle
1.8432 MHz Clock
A INPUT
B INPUT
123,093
Clock Pulses
0.5416 µs
66.667 msec.
123,093
Clock Pulses
66.667 msec.
COUT
Positive Input Signal
NOT VALID
COUT
Negative Input Signal
NOT VALID
Auto Zero
Phase
Input Signal
Integration
Phase
START
CONVERSION
CYCLE
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed number
of clock pulses
by design.
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
Reference
Voltage
Deintegration
Phase
Variable
number of
clock pulses.
At VIN MAX,
max. number of
clock pulses
=~ 246,185
Integrator Zero
Phase
Auto Zero
Phase
Fixed period of
approx.1 msec.
Stop counter upon
detection of comparator
output going from high
to low state.
REPEAT
CONVERSION
CYCLE
START INTEGRATOR ZERO CYCLE
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
5
5 Page 
3. Pick VINMAX = ±2V
For I BMAX = 20µA, applying equation (4),
RINT = 20x210-6= 100 K Ω
4. Calculate, using equation (3) for CINT:
CINT = (0.1) x (20 x 10-6/4)
~ = 0.5 µF
(assume VINTMAX = 4V)
Use CINT 0.47µF as the closest practical value.
5. Pick CREF and CAZ = 0.47 µF
6. Pick tDINT = 2 x tINT = 200 msec.
7. Calculate the value for VREF, from equation (10):
VREF = CINT . VINTMAX . RINT
tDINT MAX
= 0.5 x 10-6 x 4 x 100 x 103
200 x 10-3
= 1.00V
Design Example 3:
1. Pick resolution of 18 bit. Total number of counts during
tINT is 262,144.
2. Pick tINT = 16.66667 msec. x 10 cycles
= 0.1666667 sec.
This t INT allows clock period of 0.5425 µsec.
and still achieve 18 bits resolution.
3. Again, as shown from previous example, pick VINMAX = ±2V
For I BMAX = 20 µA,
RINT
=
2
20x10-6
=
100
KΩ
4. Next, we calculate CINT:
C INT = (0.1666667) x (20 x 10-6)/4
=~ 0.83 µF
(VINTMAX = 4.0V)
In this case, use CINT = 1.0 µF to keep
V INT < 4.0V
5. Pick CREF and CAZ = 1.0 µF
6. Select tDINT = 2 x tINT = 333.333 msec.
7. Calculate VREF as shown in the previous examples
and VREF = 1.00V
Design Example 4:
Objective: 5 1/2 digit + sign +over-range measurement.
1. Pick tINT = 133.333 msec. for 60Hz noise rejection.
(16.6667 msec. x 8 cycles)
Frequency = 1.8432 MHz
clock period = 0.5425 µsec.
During Input Integrate Phase,
total count = 133.333 x 10-3
0.5425 x 10-6
= 245776
For VINT = 4.0V, the basic resolution is
4 or 16.276 µV/count
245776
For VINMAX = 2.00V, the input resolution is
16.276 x VINMAX = 8.138 µV/count
VINTMAX
2. Pick VIN range = ± 2V
For IB = 20 µA,
RINT =
2
20 x 10-6
= 100 KΩ
3. Calculate CINT = (0.133333) x (20 x 10-6)/4 ~= 0.67 µF
4. Pick CREF = CAZ = 0.67 µF
5. Select tDINT = 2 x tINT = 266.667 msec.
6. Calculate VREF as shown in Design Example 1,
substituting the appropriate values:
VREF =
CINT . VINTMAX . RINT
tDINT MAX
~= 1.005V
ALD500AU/ALD500A/ALD500
Advanced Linear Devices
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ALD500ASC.PDF ] | |
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