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PDF AD9814 Data sheet ( Hoja de datos )
| Número de pieza | AD9814 | |
| Descripción | Complete 14-Bit CCD/CIS Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Complete 14-Bit
CCD/CIS Signal Processor
AD9814
FEATURES
14-Bit 10 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel Operation Up to 10 MSPS
1-Channel Operation Up to 7 MSPS
Correlated Double Sampling
1-6x Programmable Gain
؎300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output (8+6 Format)
3-Wire Serial Digital Interface
+3/+5 V Digital I/O Compatibility
28-Lead SOIC Package
Low Power CMOS: 330 mW (Typ)
Power-Down Mode: <1 mW
APPLICATIONS
Flatbed Document Scanners
Film Scanners
Digital Color Copiers
Multifunction Peripherals
PRODUCT DESCRIPTION
The AD9814 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture de-
signed to sample and condition the outputs of trilinear color
CCD arrays. Each channel consists of an input clamp, Corre-
lated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high performance 14-
bit A/D converter.
The CDS amplifiers may be disabled for use with sensors such
as Contact Image Sensors (CIS) and CMOS active pixel sen-
sors, which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal regis-
ters are programmed through a 3-wire serial interface, and pro-
vide adjustment of the gain, offset, and operating mode.
The AD9814 operates from a single +5 V power supply, typi-
cally consumes 330 mW of power, and is packaged in a 28-lead
SOIC.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
CML
CAPT CAPB
AVDD AVSS
DRVDD DRVSS
VINR
VING
VINB
OFFSET
CDS
9-BIT
DAC
CDS
9-BIT
DAC
CDS
9-BIT
DAC
INPUT
CLAMP
BIAS
PGA
AD9814
BANDGAP
REFERENCE
PGA
3:1
MUX
14-BIT
ADC
14 14:8 8
MUX
PGA
6
9
CONFIGURATION
REGISTER
MUX
REGISTER
RED
GREEN
BLUE
RED
GREEN
BLUE
GAIN
REGISTERS
OFFSET
REGISTERS
DIGITAL
CONTROL
INTERFACE
CDSCLK1 CDSCLK2
ADCCLK
OEB
DOUT
SCLK
SLOAD
SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD9814
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each indi-
vidual code from a line drawn from “zero scale” through “posi-
tive full scale.” The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16384 codes, respectively,
must be present over all operating ranges.
OFFSET ERROR
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.
GAIN ERROR
The last code transition should occur for an analog value
1 1/2 LSB below the nominal full-scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and converted to an equivalent voltage, using the relation-
ship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred
to the input of the AD9814 by dividing by the PGA gain.
CHANNEL-TO-CHANNEL CROSSTALK
In an ideal three channel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9814, one channel is grounded and the other two chan-
nels are exercised with full-scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAY
The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9814 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTION
Power Supply Rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.
REV. 0
–5–
5 Page 
AD9814
PGA Gain Registers
There are three PGA registers for individually programming the gain in the red, green and blue channels. Bits D8, D7 and D6 in
each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure 13 for a graph of the PGA
Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all “zeros” word corresponding to the
minimum gain setting (1x) and an all “ones” word corresponding to the maximum gain setting (5.8x).
Table IV. PGA Gain Register Settings
D8
Set to 0
0
0
D7
Set to 0
0
0
D6
Set to 0
0
0
D5
MSB
0
0
00
00
*Power-on default value.
0
0
1
1
D4 D3
00
00
•
•
•
11
11
D2 D1 D0
Gain (V/V) Gain (dB)
LSB
0 0 0* 1.0
0 01
1.013
•
•
•
1 10
5.4
1 11
5.8
0.0
0.12
•
•
•
14.6
15.25
Offset Registers
There are three PGA registers for individually programming the offset in the red, green and blue channels. Bits D8 through D0 con-
trol the offset range from –300 mV to +300 mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as
the sign bit. Table V shows the offset range as a function of the Bits D8 through D0.
D8
MSB
0
0
D7
0
0
D6
0
0
011
100
100
11
*Power-on default value.
1
Table V. Offset Register Settings
D5 D4 D3 D2 D1
00000
00000
•
•
•
11111
00000
00000
•
•
•
11111
D0 Offset (mV)
LSB
0* 0
1 +1.2
•
•
•
1 +300
00
1 –1.2
•
•
•
1 –300
REV. 0
–11–
11 Page | ||
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| PDF Descargar | [ Datasheet AD9814.PDF ] | |
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