PDF HSP50215 Data sheet ( Hoja de datos )

Número de pieza	HSP50215
Descripción	DSP Modulator Evaluation Board
Fabricantes	Intersil Corporation
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No Preview Available ! Data Sheet HSP50215 January 1999 File Number 4346.4 Digital UpConverter The HSP50215 Digital UpConverter (DUC) is a QASK/FM modulator/FDM upconverter designed for high dynamic range applications such as cellular basestations. The DUC combines shaping and interpolation filters, a complex modulator, and Timing and Carrier NCO’s into a single package. Each DUC can create a single FDM channel. Multiple DUC’s can be cascaded digitally for multi-channel applications. The HSP50215 supports both vector and FM modulation. In vector modulation mode, the DUC accepts 16-bit I and Q samples to generate virtually any quadrature AM or PM modulation format. The DUC also has two FM modulation modes. In the FM with pulse shaping mode, the 16-bit frequency samples are pulse shaped/bandlimited prior to FM modulation. No bandlimiting filter follows the FM modulator. This FM mode is useful for GMSK type modulation formats. In the FM with bandlimiting filter mode, the 16-bit frequency samples directly drive the FM modulator. The FM modulator output is filtered to limit the spectral occupancy. This FM mode is useful for analog FM or FSK modulation formats. The DUC includes an NCO driven interpolation ﬁlter, which allows the input and output sample rate to have a non- integer or variable relationship. This re-sampling feature simpliﬁes cascading modulators with sample rates that do not have harmonic or integer frequency relationships. The DUC offers digital output spectral purity that exceeds 85dB at the maximum output sample rate of 52 MSPS, for input sample rates as high as 300 KSPS. A 16-bit microprocessor compatible interface is used to load configuration and baseband data. A programmable FIFO depth interrupt simplifies the interface to the I and Q input FIFOs. Block Diagram CAS(15:0) CASZ IIN(15:0) † QIN(15:0) † IFIFO QFIFO Features • Output Sample Rates Up to 52 MSPS (48 MSPS Industrial); Input Data Rates Up to 3.25 MSPS • I/Q Vector, FM, and Shaped FM Modulation Formats • 32-Bit Programmable Carrier NCO; 30-Bit Programmable Symbol Timing NCO • Programmable I and Q, 256 Tap, Shaping FIR Filters with Interpolation by 4, 8 or 16 • Interpolation Filter Up Samples Shaping Filter Output to Output Sample Rate Under NCO Control • Processing Capable of >90dB SFDR • Cascade Input for Multiple Channel Transmissions • 16-Bit µProcessor Interface for Conﬁguration and User Data Input Applications • Single or Multiple Channel Digital Software Radio Transmitters (Wide-Band or Narrow-Band) • Base Station Transceivers • Operates with HSP50214 in Software Radio Solutions • Compatible with the HI5741 D/A Converter • HSP50215EVAL Evaluation Board Available Ordering Information PART NUMBER HSP50215VC HSP50215VI TEMP RANGE (oC) PACKAGE PKG. NO 0 to 70 100 Ld MQFP Q100 .14x20 -40 to 85 s100 Ld MQFP Q100 .14x20 † = µP CONTROL SIGNALS GAIN CTRL ++ OUT(15:0) REFCLK SYNCIN RST WR RD CE C(15:0) A(9:0) MUX FM MOD CONTROL QIN(15:0) † IIN(15:0) † CF(31:0) † SF(29:0) † I FM Q FM NCO NCO CF(31:0) † OE OFM SYNCOUT FIFORDY SAMPCLK 3-422 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 1 page HSP50215 Functional Description The HSP50215 Digital UpConverter (DUC) converts digital baseband data into modulated or frequency translated digital samples. The DUC can be conﬁgured to create any quadrature amplitude shift-keyed (QASK) data modulated signal, including QPSK, BPSK, and m-ary QAM. The DUC can also be conﬁgured to create both shaped and unﬁltered FM signals. A minimum of 16 bits of resolution is maintained throughout the internal processing. The DUC is conﬁgured via the 16-bit microprocessor data bus, using the address bus and RD, WR and CE control signals. Conﬁguration data that is loaded via this bus includes the 30-bit Sample Rate NCO center frequency, the 32-bit Carrier NCO center frequency, the modulation format, gain control, FIFO control, reset control and sync control. The I and Q baseband channels each have a 256 tap FIR ﬁlter whose coefﬁcients and conﬁguration are also programmed via the µP interface. Similarly, the control signals for the I and Q channel interpolation ﬁlters are programmed via the µP interface. Once the operational conﬁguration for the device has been set, the 16-bit µP interface is used to input the I and Q data into the associated FIFOs. The FIFOs provide the data interface between the µP and either the FM modulator or the shaping ﬁlters. Multiplexers route the I data to the FM modulator in the FM with bandlimiting ﬁlter mode. Both I and Q are routed to the 256 tap FIR shaping ﬁlters in the QASK mode. The shaping ﬁlter serves to both shape and interpolate the sample rate to 4, 8, or 16 times the input sample rate. The I shaping ﬁlter output can also be routed to the FM modulator for the FM with pulse shaping mode. Multiplexers select either the FM modulator output or the shaping ﬁlter output to be scaled and routed to the interpolation ﬁlters. The I and Q interpolation filters allow a non-integer increase in sample rate, up to the reference clock rate. The interpolation filter output data is upconverted or modulated by the Carrier NCO and multipliers. The modulated signal is added to modulated inputs from other cascaded DUC’s. The output formatter sets the output buffer state and the output data format. Programmable FIFO The Programmable FIFOs provide a data storage and interface between the microprocessor data write holding register and the shaping ﬁlter or the FM modulator. Signal routing out of the FIFO is set by the modulation format. Each FIFO has seven 16-bit registers. Figure 1 shows the conceptual details of the I and Q FIFOs. A(000) WR DFF1 R E >G DFF2 R E >G DFF3 R E >G DFF4 R E >G † ALL REGISTERS ARE CLOCKED AT REFCLK UNLESS SHOWN OTHERWISE IIN(15:0) WRITE SHIFT ENABLE RR R R R EE E E E >G >G >G >G >G WR R E >G R E >G R E >G ZERO’S A(2:0) 8:1 MUX RTH(2:0) IFIFO(15:0) FM ENABLED QIN(15:0) 8:1 MUX FIFORDY QFIFO(15:0) RR EE >G >G WR R RRR E EEE >G >G >G >G WRITE SHIFT ENABLE R E >G A(001) WR DFF1 R E >G DFF2 R E >G DFF3 R E >G DFF4 R E >G R E >G FIGURE 1. I AND Q FIFO BLOCK DIAGRAM WR REFCLK 1234 DLY DATA DFF 1 DFF 2 DFF 3 DFF 4 WR SHFT EN REG1 FIFO NEEDS FIFORDY MORE DATA FIFO NEEDS MORE DATA FIGURE 2. FIFORDY AND DATA DELAY TIMING 3-426 5 Page HSP50215 Cascade Input The cascade input allows multiple modulated signals to be summed together prior to routing to a DAC. Figure 12 is a block diagram of the cascade circuitry. CAS(15:0) is the input when cascading with other DUC’s. The CASZ is used to zero the CAS(15:0) input when it is not used. Both the CAS(15:0) and the modulator data path are registered, prior to summation. The output of the summation is saturated to prevent roll-over. 16 CAS(15:0) CASZ R E >G ∑ SATURATE 16 CIRCUITRY FROM MODULATOR † ALL REGISTERS ARE CLOCKED AT REFLCK 16 R E >G FIGURE 12. CASCADE INPUT BLOCK DIAGRAM Output Formatter The output can be either twos complement or offset binary format. The OFM signal is used to select the output format. OFM = 1 is twos complement. OFM = 0 is Offset Binary format. The OE signal is used to enable the data bus output. OE = 0 enables the output. NOTE: The HSP43216 can be used to double the output sample rate of the DUC, in applications where a higher sample rate into the DAC is required. Microprocessor Interface The microprocessor interface is a memory mapped direct access interface. The control pins are RD, WR and CE. The 10-bit address bus is A(9:0) [address space is 1024 words] and the 16-bit data bus is C(15:0). The CE signal gates the RD and WR. Care must be taken in changing the address and data lines, as the addresses are updated asynchronous to REFCLK except in the cases noted in the Microprocessor Write Section. Most addresses are intended to be programmed after RESET and before the Start Sequence, and left alone after that. See the RESET and Start Sequence sections from more details on initiating operation of the part. Reads are asynchronous to clock. The shaping ﬁlter coefﬁcients cannot be read. See the Conﬁguration Control Register Bit Deﬁnitions section for programming details of the 14 Control Words and the 512 Coefﬁcient Registers. Microprocessor Write The Microprocessor Write Interface is used for loading data into the DUC control registers. Write registers are accessed via the 10-bit address bus (A9:0) and the 16-bit data bus (C15:0). The address map for these registers is given in the Configuration Control Register Bit Definition section. Configuration data is written into the HSP50215 by setting up the address (A9:0) and data (C15:0) and generating a rising edge on WR. A DUC configuration sequence is shown in Figure 13. Figure 13 assumes that CE is asserted. The filter coefficients for the shaping filter are loaded in a similar manner into Control Word addresses 512 - 1023. WR A(10:0) 2 3 4 5 16 17 18 19 22 23 C(15:0) LOAD CONFIGURATION DATA FIGURE 13. CONTROL REGISTER LOADING SEQUENCE The Re-Sampler NCO Center Frequency data is double buffered and transfers from the Microprocessor Interface holding registers to the Center Frequency Register on the assertion of SYNCIN or a Write to Conﬁguration Control Word 3. The timing waveforms for this process are shown in Figure 14. REFCLK WR SYNCIN A0-2 02 03 C0-7 MSB LSB CW02 MSB CW03 LSB SR(29:0) NEW SR VALUE FIGURE 14. RESAMPLER CENTER FREQUENCY CONTROL REGISTER LOADING SEQUENCE When SYNCIN is sampled “high” by the rising edge of clock, the contents of the holding registers are transferred to the Sample Center Frequency Register. Caution should be taken when using the SYNCIN since the holding register contents will be transferred to the Sample Center Frequency Register whenever SYNCIN is asserted (and external sync is selected via CW22). Shaping filter I coefficients are loaded from the first coefficient (C0) in address 0x200h to the last address in 0x2FFh. Because interpolation by 16 is possible, the coefﬁcient addresses are structured in blocks of 16, one address for each phase of the interpolation. With a 256 tap ﬁlter using an interpolation of 16, there are 16 multiplies required to implement the ﬁlter. Tables 4 and 5 detail the coefﬁcient address allocation, with the Interpolation Phase indicated by the IP number on the left, and the multiplier number indicated by the numbers 0 through 15 across the top. 3-432 11 Page

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