PDF HT48R06A-1 Data sheet ( Hoja de datos )

Número de pieza	HT48R06A-1
Descripción	8-Bit OTP Microcontroller
Fabricantes	Holtek Semiconductor Inc
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No Preview Available ! Preliminary HT48R06A-1 8-Bit OTP Microcontroller Features · Operating voltage: fSYS=4MHz: 3.3V~5.5V fSYS=8MHz: 4.5V~5.5V · 13 bidirectional I/O lines · An interrupt input shared with an I/O line · 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler · On-chip crystal and RC oscillator · Watchdog timer · 1024´14 program memory PROM · 64´8 data memory RAM · Buzzer driving pair and PFD supported · Halt function and wake-up feature reduce power consumption · Up to 0.5ms instruction cycle with 8MHz system clock at VDD=5V · Allinstructionsinoneortwomachinecycles · 14-bit table read instruction · Two-level subroutine nesting · Bit manipulation instruction · 63 powerful instructions · Low voltage reset function · 18-pin DIP/SOP package General Description The device is an 8-bit high performance RISC-like microcontroller designed for multi- ple I/O product applications. The device is par- ticularly suitable for use in products such as remote controllers, fan/light controllers, wash- ing machine controllers, scales, toys and vari- ous subsystem controllers. A halt feature is included to reduce power consumption. The program and option memories can be elec- trically programmed, making the microcontrol- ler suitable for use in product development. 1 February 25, 2000 1 page Preliminary HT48R06A-1 A.C. Characteristics Ta=25°C Symbol fSYS1 fSYS2 fTIMER tWDTOSC tWDT1 tWDT2 tRES tSST tINT Parameter System Clock (Crystal OSC) Test Conditions VDD Conditions 3.3V ¾ 5V ¾ System Clock (RC OSC) 3.3V 5V ¾ ¾ 3.3V Timer I/P Frequency (TMR) 5V ¾ ¾ Watchdog Oscillator 3.3V 5V ¾ ¾ Watchdog Time-out Period 3.3V Without WDT (RC) 5V prescaler Watchdog Time-out Period (System Clock) ¾ Without WDT prescaler External Reset Low Pulse Width ¾ ¾ System Start-up Timer Period ¾ Power-up, reset or wake-up from Halt Interrupt Pulse Width ¾ ¾ Min. 400 400 400 400 0 0 43 35 11 9 ¾ 1 ¾ 1 Typ. ¾ ¾ ¾ ¾ ¾ ¾ 86 65 22 17 1024 ¾ 1024 ¾ Max. Unit 4000 kHz 8000 kHz 4000 kHz 4000 kHz 4000 kHz 4000 kHz 168 ms 130 ms 43 ms 35 ms ¾ tSYS ¾ ms ¾ tSYS ¾ ms 5 February 25, 2000 5 Page Preliminary HT48R06A-1 request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a sub- routine call to location 04H will occur. The in- terrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the "RETI" instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, "RET" or "RETI" may be invoked. RETI will set the EMI bit to en- able an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are en- abled. In the case of simultaneous requests the following table shows the priority that is ap- plied. These can be masked by resetting the EMI bit. No. Interrupt Source Priority Vector a External Interrupt 1 04H b Timer/event Counter Overflow 2 08H The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), en- able timer/event counter bit (ETI), enable ex- ternal interrupt bit (EEI) and enable master interrupt bit (EMI) constitute an interrupt con- trol register (INTC) which is located at 0BH in the data memory. EMI, EEI, ETI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the "CALL subroutine" within the inter- rupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will Register Bit No. 0 1 INTC (0BH) 2 3 4 5 6 7 Label EMI EEI ETI ¾ EIF TF ¾ ¾ Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled) Controls the timer/event counter interrupt (1= enabled; 0= disabled) Unused bit, read as "0" External interrupt request flag (1= active; 0= inactive) Internal timer/event counter request flag (1= active; 0= inactive) Unused bit, read as "0" Unused bit, read as "0" INTC register 11 February 25, 2000 11 Page

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