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PDF HT9480 Data sheet ( Hoja de datos )
| Número de pieza | HT9480 | |
| Descripción | Pager Controller | |
| Fabricantes | Holtek Semiconductor Inc | |
| Logotipo |  |
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HT9480
Pager Controller
Features
• Operating voltage: 2.2V~3.5V
• Low power crystal oscillator control
– 512, 1200, or 2400 bps data rate operation
• Decodes CCIR Radio-paging Code
No.1 (POCSAG Code)
• 2-bit random and optional 4-bit burst error
correction
• Improved synchronization algorithm
• Supports up to 6 independently program-
mable user addresses and 6 user frames
• Three RF power on timing control pins
• Single crystal for all available baud rate
(76.8kHz crystal)
• Battery low indication (external detector)
• Battery fail interrupt and data ready
interrupt
• 8K×16 program ROM
• 416×8 data RAM
• 35×4 LCD display
• 7 input lines and 10 bidirectional I/O lines
• 8-bit programmable timer for RTC
interrupt
• 8-bit programmable timer/event counter
and overflow interrupt
• 8-bit programmable tone generator with
buzzer output
• Watchdog timer
• Halt function and wake-up feature reduce
power consumption
• 63 powerful instructions, most instructions
in one machine cycle
• Eight-level subroutine nesting
• Table read instruction
• Inverted or non-inverted input signal
selection for decoder input
• 80-pin LQFP package
General Description
The HT9480 is a high performance pager con-
troller. The built-in single cycle instructions
(16-bit wide) and two-stage pipeline architec-
ture of the HT9480 account for its high perform-
ance. The controller contains a full function
pager decoder (POCSAG code) at 512, 1200, or
2400 bits per second data rate and an LCD
display driver with a 35×4 dot output.
1 23th Feb ’98
1 page  
HT9480
Absolute Maximum Ratings*
Supply Voltage .............................. –0.3V to 5.5V
Input Voltage..................VSS–0.3V to VDD+0.3V
Storage Temperature................. –50°C to 125°C
Operating Temperature............... –25°C to 85°C
*Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied and exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. Characteristics
(Ta=25°C)
Symbol
Parameter
VDD
IDD
Operating Voltage
Operating Current
ISTB1
Standby Current 1
Test Conditions
VDD
Conditions
— 3V application
3V
No load,
fsys=153.6kHz
3V
No load, System
HALT (Watchdog ON)
Min.
2.2
—
—
Typ. Max. Unit
3.0 3.5 V
300 — µA
200 — µA
ISTB2
VIL
Standby Current 2
Input Low Voltage for
Input Port and I/O Port
3V
No load, System
HALT (Watchdog OFF)
—
—
1
µA
3V —
0—1 V
VIH
Input High Voltage for
Input Port and I/O Port
3V
—
2.2 — 3 V
VIL1
VIH1
VIL2
VIH2
IOL
IOH
IOL
Input Low Voltage
(RES,TMR1,BAL)
Input High Voltage
(RES,TMR1,BAL)
Input Low Voltage (BAF)
Input High Voltage (BAF)
I/O Port Sink Current
I/O Port Source Current
Segment 0-34 Output
Sink Current
3V —
3V —
3V —
3V —
3V VOL=0.3V
3V VOH=2.7V
3V VOL=0.3V
0—1 V
2.2 — 3 V
0 — 0.9 V
1.3 — 3 V
1.7 3.4 — mA
–1 –1.9 — mA
20 44 — µA
IOH
Segment 0-34 Output
Source Current
3V VOH=2.7V
–20 –38 — µA
IOL BZ, Sink Current
IOH BZ, Source Current
3V VOL=0.3V
3V VOH=2.7V
1 2.5 — mA
–1 –2 — mA
5 23th Feb ’98
5 Page 
HT9480
ters are from 20H to 3FH, where each bank
points to the same location. The other spaces,
namely 0CH, 0FH, 13H, the high nibble of 16H,
17H, and 18H~1CH, are all reserved for future
expansion usage; reading these locations will
get an “00H” value.
On the other hand, the general purpose data
memory, divided into three banks (bank 0, bank
1, and bank 27), is used for data, control infor-
mation, and LCD display control under instruc-
tion commands. The banks in the RAM are all
addressed from 40H to FFH, and are selected by
setting the value (“00H”: bank 0; “01H”: bank 1;
“1BH”: bank 27) of the bank pointer (BP;04H).
The bank27 memory is used for LCD display
mapping and the decoder configuration RAM
mapping. The spaces from 4FH to BFH and
from E3H to FFH, and the high nibble part from
C0H to E2H in bank 27 are all reserved for
future expansion usage; reading these locations
will derive “00H”.
The special registers, global data registers and
general data memory can directly perform
arithmetic, logic, increment, decrement, and ro-
tate operations. Each bit in the RAM can be set
and reset by “SET [m].i” and “CLR [m].i”, and
can also be indirectly accessible through the
memory pointer registers (MP0;01H, MP1;03H).
Of the special addresses, 1DH and 1FH cannot
directly do all these operations, because they
are not read and write accessible addresses.
1DH is a write-only address, 1FH a read-only
address, but these two addresses namely, 1DH
and 1FH can only perform operations by using
the “MOV” instruction.
Indirect addressing register
IARx (IAR0;00H, IAR1;02H) are indirect ad-
dress registers that are not physically imple-
mented. Any read/write operation of the IARx
accesses the data memory pointed to by MPx
(MP0;01H, MP1;03H). Reading the indirect ad-
dressing register itself will indirectly derive
00H, while writing the indirect addressing reg-
ister indirectly will lead to no operations. (IAR0,
MP0) is indirectly addressable in bank 0, but
(IAR1, MP1) is available for all banks.
Accumulator – ACC
The accumulator (ACC) relates to the ALU opera-
tions. It is also mapped to location 05H of the data
memory and is capable of carrying out immediate
data operations. Data movement between these
two data memories has to pass through the ACC.
Arithmetic and logic unit – ALU
This circuit performs 8-bit arithmetic and logic
operations, and provides the following functions:
• Arithmetic operation (ADD, ADC, SUB, SBC, DAA)
• Logic operation (AND, OR, XOR, CPL)
• Rotation (RL, RR, RLC, RRC)
• Increment and decrement (INC, DEC)
• Branch decision (SZ, SNZ, SIZ, SDZ, etc.)
The ALU not only saves the results of data
operation, but also changes the contents of the
status register.
Status register – STATUS
The status register (0AH) is 8-bit wide. It contains
a zero flag (Z), a carry flag (C), an auxiliary carry
flag (AC), an overflow flag (OV), a powerdown flag
(PD), and a WDT time-out flag (TO). The status
register not only records the status information,
but also controls the operation sequence.
The status register, like most other registers,
can be altered by instructions except for the TO
and PD flags. Any data written into the status
register will not change TO or PD. It should be
noted that operations related to the status reg-
ister may derive different results from those
intended. For example, clearing the status reg-
ister CLR [0AH] has no effect on the TO and PD
flags, and the value of the zero flag is also “1”,
i.e., UU0100 is the data in the register, where
the value of U is an unchanged value.
The Z, OV, AC, and C flags generally reflect the
status of the latest operations.
On entering an interrupt sequence or executing
a subroutine call, the status register will not be
automatically pushed onto the stack. If the con-
tents of the status is important, and if the sub-
routine may corrupt the status register, the
programmer should take precautions to save it
properly.
11 23th Feb ’98
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT9480.PDF ] | |
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